Reveal Troubleshooting Guide - Lattice Semiconductor

Reveal Troubleshooting Guide EDIF Support
EDIF Support
� User-defined enumerated types, with the exception of arrays of std_logic
or std_ulogic
You can still use these types in the design, but signals of these types are not
available for tracing or triggering. VHDL signals that are traced or triggered
must be of types std_logic, std_logic_vector, std_ulogic, std_ulogic_vector,
bit, or bit_vector. In addition, subtypes of std_ulogic_vector or
std_logic_vector are supported, as well as user-defined types that are arrays
of std_logic or std_ulogic.
The EDIF flow is fully supported in Reveal. However, you must be aware of
the following:
� The Reveal Inserter must be started from a Project Navigator project. In
order to use the EDIF flow with the Reveal Inserter, you must start the
Reveal Inserter from a Project Navigator EDIF project. You cannot start
the EDIF flow from a Project Navigator project that is schematic, VHDL/
schematic, VHDL, Verilog/schematic, or Verilog.
� In the EDIF flow, the representation in the Reveal Inserter is of the EDIF
hierarchy and signal names. Buses appear as individual signals instead of
buses, as in the RTL flow.
Reveal Troubleshooting Guide 2