epdf.pub_nanotechnology-and-nanoelectronics-materials-devic

1.2 Moore’s Law and the SIA Roadmap 3
Table 1.1
Selected roadmap milestones
Year 1997 1999 2001 2003 2006 2009 2012
Dense lines, nm 250 180 150 130 100 70 50
Iso. lines (MPU gates), 200 140 120 100 70 50 35
nm
DRAM memory (introduced)
267 M 1.07 G [1.7 G] 4.29 G 17.2 G 68.7 G 275 G
MPU: transistors per 11 M 21 M 40 M 76 M 200 M 520 M 1.4 G
chip
Frequency, MHz 750 1200 1400 1600 2000 2500 3000
Minimum supply voltage
V dd , V
1.8–
2.5
1.5–
1.8
1.2–
1.5
1.2–
1.5
0.9–
1.2
0.6–
0.9
0.5–
0.6
Max. wafer diameter, mm 200 300 300 300 300 450 450
DRAM chip size, mm 2 280 400 445 560 790 1120 1580
(introduced)
Lithography field size,
mm 2 22·22
484
25·32
800
25·34
850
25·36
900
25·40
1000
25·44
1100
25·52
1300
Maximum wiring levels 6 6–7 7 7 7–8 8–9 9
Maximum mask levels 22 22–24 23 24 24–26 26–28 28
Density of electrical 2080 1455 [1310] 1040 735 520 370
duced), 1 / m 2
DRAM defects (intro-
MPU: microprocessor unit, DRAM: dynamic random access memory