Introduction to Microcontrollers

2.1. PROCESSOR CORE 17
Example: Some opcodes of the ATmega16
The ATmega16 is an 8-bit harvard RISC controller with a fixed opcode size of 16 or in some
cases 32 bits. The controller has 32 general purpose registers. Here are some of its instructions
with their corresponding opcodes.
instruction result operand conditions opcode
ADD Rd, Rr Rd + Rd ← Rr 0 ≤ d ≤ 31, 0000 11rd dddd rrrr
0 ≤ r ≤ 31
AND Rd, Rr Rd ← Rd & Rr 0 ≤ d ≤ 31, 0010 00rd dddd rrrr
0 ≤ r ≤ 31
NOP 0000 0000 0000 0000
LDI Rd, K Rd ← K 16 ≤ d ≤ 31, 1110 KKKK dddd KKKK
0 ≤ K ≤ 255
LDS Rd, k Rd ← [k] 0 ≤ d ≤ 31, 1001 000d dddd 0000
0 ≤ k ≤ 65535 kkkk kkkk kkkk kkkk
Note that the LDI instruction, which loads a register with a constant, only operates on the upper
16 out of the whole 32 registers. This is necessary because there is no room in the 16 bit to
store the 5th bit required to address the lower 16 registers as well, and extending the operation
to 32 bits just to accommodate one more bit would be an exorbitant waste of resources.
The last instruction, LDS, which loads data from the data memory, actually requires 32 bits
to accommodate the memory address, so the controller has to perform two program memory
accesses to load the whole instruction.
what you need. For instance, the 10 lines of ATmega16 RISC code require 20 byte of code (each
instruction is encoded in 16 bits), whereas the 68030 instruction fits into 4 bytes. So here, the 68030
clearly wins. If, however, you only need instructions already provided by an architecture with short
opcodes, it will most likely beat a machine with longer opcodes. We say “most likely” here, because
CISC machines with long opcodes tend to make up for this deficit with variable size instructions. The
idea here is that although a complex operation with many operands may require 32 bits to encode,
a simple NOP (no operation) without any arguments could fit into 8 bits. As long as the first byte
of an instructions makes it clear whether further bytes should be decoded or not, there is no reason
not to allow simple instructions to take up only one byte. Of course, this technique makes instruction
fetching and decoding more complicated, but it still beats the overhead of a large fixed-size opcode.
RISC machines, on the other hand, tend to feature short but fixed-size opcodes to simplify instruction
decoding.
Obviously, a lot of space in the opcode is taken up by the operands. So one way of reducing the
instruction size is to cut back on the number of operands that are explicitly encoded in the opcode.
In consequence, we can distinguish four different architectures, depending on how many explicit
operands a binary operation like ADD requires:
Stack Architecture: This architecture, also called 0-address format architecture, does not have any
explicit operands. Instead, the operands are organized as a stack: An instruction like ADD takes
the top-most two values from the stack, adds them, and puts the result on the stack.
Accumulator Architecture: This architecture, also called 1-address format architecture, has an ac-