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Introduction to Microcontrollers

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2.2. MEMORY 31<br />

a matter of minutes. Separate memory addressing, on the other hand, comes with an implicit<br />

protection against access <strong>to</strong> the wrong type of memory.<br />

When accessing byte-addressed memory word-wise, there is a special pitfall <strong>to</strong> be considered:<br />

Suppose a 16 bit controller writes a word (two bytes) in<strong>to</strong> SRAM, say at address 0x0100. The word<br />

consists of a low and a high byte. Now, in what order are the bytes <strong>to</strong> be written? There are two<br />

variants: the low byte could go <strong>to</strong> 0x0100 and the high byte <strong>to</strong> the next address (0x0101), or the other<br />

way around. That is the problem of endianness:<br />

Big Endian: Big Endian architectures s<strong>to</strong>re the high byte first. So, if you write the word 0x1234 <strong>to</strong><br />

address 0x0100, the high byte 0x12 goes <strong>to</strong> address 0x0100, and the low byte 0x34 <strong>to</strong> address<br />

0x0101. The name is derived from this order: The Big End of the word is s<strong>to</strong>red first – therefore,<br />

it is called Big Endian.<br />

Little Endian: Little Endian architectures access memory the other way around (Little End of the<br />

word first). Here, the low byte is s<strong>to</strong>red first. Writing 0x1234 at address 0x0100 on a little<br />

endian architecture writes 0x34 <strong>to</strong> address 0x0100 and 0x12 <strong>to</strong> address 0x0101.<br />

Note carefully, however, that this difference in the ordering of high and low is only relevant on a<br />

byte level. The bits within a byte are numbered from right <strong>to</strong> left on both architectures. So, the least<br />

significant bit is always the rightmost one.<br />

2.2.4 Exercises<br />

Exercise 2.2.1 Assume that the values (1, 2, 3, 4) are s<strong>to</strong>red at the memory (byte) addresses 0, 1, 2, 3.<br />

You load the word from address 1 in<strong>to</strong> register R1 (assume that unaligned access is possible). Which<br />

(hexadecimal) value does R1 have if the architecture is big endian?<br />

Exercise 2.2.2 What are the advantages of PROM over ROM? Are there any disadvantages?<br />

Exercise 2.2.3 Why do EPROMs have a window, while EEPROMs do not have a window? What is<br />

the window used for?<br />

Exercise 2.2.4 What is the difference between an EEPROM and a Flash-EEPROM?<br />

Exercise 2.2.5 Assume you have an EEPROM that is specified for 100,000 write cycles. You want<br />

<strong>to</strong> s<strong>to</strong>re the daily exchange rate for some currency. For how many years can you use the EEPROM?<br />

Would it be sensible <strong>to</strong> put the EEPROM in<strong>to</strong> a socket <strong>to</strong> be able <strong>to</strong> exchange it easily? What if you<br />

have <strong>to</strong> update the exchange rate hourly?<br />

Exercise 2.2.6 What are the advantages and disadvantages of a RAM compared <strong>to</strong> an EEPROM?<br />

Exercise 2.2.7 Why do microcontrollers use SRAMs and not DRAMs?<br />

Exercise 2.2.8 Why does the NVRAM not copy every write access in<strong>to</strong> the EEPROM? Would that<br />

not be more secure?<br />

Exercise 2.2.9 When is an OTP memory useful? Would you put a controller with OTP memory in<strong>to</strong><br />

a cell phone?<br />

Exercise 2.2.10 Assume that you have the loop for (i=100; i>=0; i--) in your C program.<br />

The loop variable i is inadvertently s<strong>to</strong>red in EEPROM instead of SRAM. To make things worse, you<br />

implemented the loop with an unsigned variable i, so the loop will not s<strong>to</strong>p. Since the access is now<br />

<strong>to</strong> the slow EEPROM, each iteration of the loop takes 10 ms.

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