Introduction to Microcontrollers

More documents

Recommendations

Info

20 CHAPTER 2. MICROCONTROLLER COMPONENTS immediate/literal: Here, the operand is a constant. From the application programmer’s point of view, processors may either provide a distinct instruction for constants (like the LDI —load immediate— instruction of the ATmega16), or require the programmer to flag constants in the assembler code with some prefix like #. register: Here, the operand is the register that contains the value or that should be used to store the result. direct/absolute: The operand is a memory location. register indirect: Here, a register is specified, but it only contains the memory address of the actual source or destination. The actual access is to this memory location. autoincrement: This is a variant of indirect addressing where the contents of the specified register is incremented either before (pre-increment) or after (post-increment) the access to the memory location. The post-increment variant is very useful for iterating through an array, since you can store the base address of the array as an index into the array and then simply access each element in one instruction, while the index gets incremented automatically. autodecrement: This is the counter-part to the autoincrement mode, the register value gets decremented either before or after the access to the memory location. Again nice to have when iterating through arrays. displacement/based: In this mode, the programmer specifies a constant and a register. The contents of the register is added to the constant to get the final memory location. This can again be used for arrays if the constant is interpreted as the base address and the register as the index within the array. indexed: Here, two registers are specified, and their contents are added to form the memory address. The mode is similar to the displacement mode and can again be used for arrays by storing the base address in one register and the index in the other. Some controllers use a special register as the index register. In this case, it does not have to be specified explicitly. memory indirect: The programmer again specifies a register, but the corresponding memory location is interpreted as a pointer, i.e., it contains the final memory location. This mode is quite useful, for example for jump tables. Table 2.2 shows the addressing modes in action. In the table, M[x] is an access to the memory address x, d is the data size, and #n indicates a constant. The notation is taken from [HP90] and varies from controller to controller. As we have already mentioned, CISC processors feature more addressing modes than RISC processors, so RISC processors must construct more complex addressing modes with several instructions. Hence, if you often need a complex addressing mode, a CISC machine providing this mode may be the wiser choice. Before we close this section, we would like to introduce you to a few terms you will often encounter: • An instruction set is called orthogonal if you can use every instruction with every addressing mode. • If it is only possible to address memory with special memory access instructions (LOAD, STORE), and all other instructions like arithmetic instructions only operate on registers, the architecture is called a load/store architecture. • If all registers have the same function (apart from a couple of system registers like the PC or the SP), then these registers are called general-purpose registers.
2.1. PROCESSOR CORE 21 2.1.3 Exercises addressing mode example result immediate ADD R1, #5 R1 ← R1 + 5 register ADD R1, R2 R1 ← R1 + R2 direct ADD R1, 100 R1 ← R1 + M[100] register indirect ADD R1, (R2) R1 ← R1 + M[R2] post-increment ADD R1, (R2)+ R1 ← R1 + M[R2] R2 ← R2 + d pre-decrement ADD R1, −(R2) R2 ← R2 − d R1 ← R1 + M[R2] displacement ADD R1, 100(R2) R1 ← R1 + M[100 + R2] indexed ADD R1, (R2+R3) R1 ← R1 + M[R2+R3] memory indirect ADD R1, @(R2) R1 ← R1 + M[M[R2]] Table 2.2: Comparison of addressing modes. Exercise 2.1.1 What are the advantages of the Harvard architecture in relation to the von Neumann architecture? If you equip a von Neumann machine with a dual-ported RAM (that is a RAM which allows two concurrent accesses), does this make it a Harvard machine, or is there still something missing? Exercise 2.1.2 Why was RISC developed? Why can it be faster to do something with several instructions instead of just one? Exercise 2.1.3 What are the advantages of general-purpose registers as opposed to dedicated registers? What are their disadvantages? Exercise 2.1.4 In Section 2.1.2, we compared different address formats. In our example, the accumulator architecture requires the least instructions to execute the task. Does this mean that accumulator architectures are particularly code-efficient? Exercise 2.1.5 What are the advantages and drawbacks of a load/store architecture? Exercise 2.1.6 Assume that you want to access an array consisting of 10 words (a word has 16 bit) starting at memory address 100. Write an assembler program that iterates through the array (pseudocode). Compare the addressing modes register indirect, displacement, auto-increment, and indexed. Exercise 2.1.7 Why do negative numbers in an arithmetic shift left (ASL) stay negative as long as there is no overflow, even though the sign bit is not treated any special? Can you prove that the sign bit remains set in an ASL as long as there is no overflow? Is it always true that even with an overflow the result will remain correct (modulo the range)?
Page 1 and 2: Introduction to Microcontrollers Co
Page 3 and 4: 2.7.2 Power Consumption and Sleep .
Page 6 and 7: Preface This text has been develope
Page 8 and 9: 2 CHAPTER 1. MICROCONTROLLER BASICS
Page 16 and 17: 10 CHAPTER 1. MICROCONTROLLER BASIC
Page 18 and 19: 12 CHAPTER 2. MICROCONTROLLER COMPO
Page 76 and 77:
70 CHAPTER 2. MICROCONTROLLER COMPO
Page 78 and 79:
72 CHAPTER 2. MICROCONTROLLER COMPO
Page 80 and 81:
74 CHAPTER 3. COMMUNICATION INTERFA
Page 82 and 83:
Page 84 and 85:
Page 86 and 87:
Page 88 and 89:
Page 90 and 91:
Page 92 and 93:
Page 94 and 95:
Page 96 and 97:
90 CHAPTER 4. SOFTWARE DEVELOPMENT
Page 98 and 99:
Page 100 and 101:
Page 102 and 103:
Page 104 and 105:
Page 106 and 107:
Page 108 and 109:
Page 110 and 111:
Page 112 and 113:
Page 114 and 115:
Page 116 and 117:
Page 118 and 119:
Page 120 and 121:
Page 122 and 123:
Page 124 and 125:
Page 126 and 127:
Page 128 and 129:
Page 130 and 131:
Page 132 and 133:
Page 134 and 135:
Page 136 and 137:
130 CHAPTER 5. HARDWARE A somewhat
Page 138 and 139:
132 CHAPTER 5. HARDWARE This effect
Page 140 and 141:
134 CHAPTER 5. HARDWARE B A (a) A B
Page 142 and 143:
136 CHAPTER 5. HARDWARE e a f g d F
Page 144 and 145:
138 CHAPTER 5. HARDWARE new value f
Page 146 and 147:
140 CHAPTER 5. HARDWARE Relays come
Page 148 and 149:
142 CHAPTER 5. HARDWARE N S N S Fig
Page 150 and 151:
144 CHAPTER 5. HARDWARE motor speed
Page 152 and 153:
146 CHAPTER 5. HARDWARE A B UM moto
Page 154 and 155:
148 CHAPTER 5. HARDWARE requires a
Page 156 and 157:
150 CHAPTER 5. HARDWARE Half- and m
Page 158 and 159:
152 CHAPTER 5. HARDWARE Stepper Mot
Page 160 and 161:
154 CHAPTER 5. HARDWARE
Page 162 and 163:
156 APPENDIX A. TABLE OF ACRONYMS E
Page 164 and 165:
158 APPENDIX A. TABLE OF ACRONYMS T
Page 166 and 167:
160 INDEX Ankerspule (armature coil
Page 168 and 169:
162 INDEX Embedded Processor, 7 Emb
Page 170 and 171:
164 INDEX non-volatile RAM, 29 NVRA
Page 172 and 173:
166 INDEX source input, 38 source o
Page 174 and 175:
168 INDEX
show all

Introduction to Microcontrollers

Create successful ePaper yourself

Delete template?

Save as template?