IRF9540, RF1S9540SM 19A, 100V, 0.200 Ohm, P ... - EBG - Darmstadt

19A, 100V, 0.200 Ohm, P-Channel Power
MOSFETs
These are P-Channel enhancement mode silicon gate power
field effect transistors. They are advanced power MOSFETs
designed, tested, and guaranteed to withstand a specified
level of energy in the breakdown avalanche mode of
operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching
convertors, motor drivers, relay drivers, and drivers for high
power bipolar switching transistors requiring high speed and
low gate drive power. They can be operated directly from
integrated circuits.
Formerly Developmental Type TA17521.
Ordering Information
PART NUMBER PACKAGE BRAND
IRF9540 TO-220AB IRF9540
RF1S9540SM TO-263AB RF1S9540
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-263AB variant in the tape and reel, i.e., RF1S9540SM9A.
Packaging
DRAIN (FLANGE)
Data Sheet January 2002
Features
• 19A, 100V
• rDS(ON)
= 0.200Ω
IRF9540, RF1S9540SM
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
JEDEC TO-220AB JEDEC TO-263AB
SOURCE
DRAIN
GATE
GATE
SOURCE
©2002 Fairchild Semiconductor Corporation IRF9540, RF1S9540SM Rev. B
G
D
S
DRAIN
(FLANGE)

Absolute Maximum Ratings TC
= 25
o
C, Unless Otherwise Specified
IRF9540,
RF1S9540SM UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS
Drain to Gate Voltage (RGS
= 20kΩ)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
TC
= 100oC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-100
-100
-19
-12
-76
± 20
150
1
V
V
A
A
A
V
W
W/ oC
Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ,
TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
960
-55 to 175
300
260
mJ
oC
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ
= 25oC
to 150oC.
Electrical Specifications
TC
= 25oC,
Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS
Gate to Threshold Voltage VGS(TH)
Zero Gate Voltage Drain Current IDSS
On-State Drain Current (Note 2) ID(ON)
Gate to Source Leakage Current IGSS
Drain to Source On Resistance (Note 2) rDS(ON)
Forward Transconductance (Note 2) g fs V
Turn-On Delay Time td(ON)
Rise Time tr
Turn-Off Delay Time td(OFF)
Fall Time tf
Total Gate Charge
(Gate to Source + Gate to Drain)
Q
g(TOT)
Gate to Source Charge Qgs
Gate to Drain “Miller” Charge Qgd
Input Capacitance CISS
Output Capacitance COSS
Reverse Transfer Capacitance CRSS
Internal Drain Inductance LD
Internal Source Inductance L
S
Thermal Resistance Junction to Case RθJC
Thermal Resistance Junction to Ambient RθJA
IRF9540, RF1S9540SM
ID
= -250µ
A, VGS
= 0V (Figure 10) -100 - - V
VGS
= VDS,
ID
= -250µ
A -2 - -4 V
VDS
= Rated BVDSS,
VGS
= 0V - - -25
VDS
= 0.8 x Rated BVDSS,
VGS
= 0V, TC
= 125oC
- - -250
VDS
> ID(ON)
x rDS(ON)
MAX,
VGS
= -10V -19 - - A
VGS
= ± 20V - -
©2002 Fairchild Semiconductor Corporation IRF9540, RF1S9540SM Rev. B
µ A
µ A
± 100 nA
ID
= -10A, VGS
= -10V (Figures 8, 9) - 0.150 0.200 Ω
DS > ID(ON)
x rDS(ON)
MAX,
ID
= -6A
(Figure 12)
5 7 - S
VDD
= -50V, ID
≈19A,
RG
= 9.1Ω,
RL
= 2.3Ω,
VGS
= -10V, (Figures 17, 18)
MOSFET Switching Times are Essentially
Independent of Operating Temperature
VGS
= -10V, ID
= -19A, VDS
= 0.8 x Rated BVDSS,
Ig(REF)
= -1.5mA (Figures 14, 19, 20)
Gate Charge is Essentially Independent of
Operating Temperature
VDS
= -25V, VGS
= 0V, f = 1MHz
(Figure 11)
Measured From the
Contact Screw on Tab to
the Center of Die
Measured From the Drain
Lead, 6mm (0.25in) from
Package to the Center of
Die
Measured From the
Source Lead, 6mm
(0.25in) From Package to
Source Bonding Pad
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
D
G
- 16 20 ns
- 65 100 ns
- 47 70 ns
- 28 70 ns
- 70 90 nC
- 14 - nC
- 56 - nC
- 1100 - pF
- 550 - pF
- 250 - pF
- 3.5 - nH
- 4.5 - nH
- 7.5 - nH
- - 1
Typical Socket Mount - - 62.5
L D
L S
S
oC/W
oC/W

Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current I
SD
Pulse Source to Drain Current
(Note 3)
I
SDM
Source to Drain Diode Voltage (Note 2) VSD
Reverse Recovery Time trr
Reverse Recovery Charge QRR
NOTES:
2. Pulse test: pulse width ≤ 300µ
s, duty cycle ≤ 2%.
Modified MOSFET Symbol
Showing the Integral Reverse
P-N Junction Diode
TC
= 25oC,
I
T
J
= 150oC,
I
TJ
= 150oC,
I
SD
SD
SD
- - -19 A
- - -76 A
= -19A, VGS
= 0V (Figure 13) - - -1.5 V
= 19A, dISD/dt
= 100A/ µ s - 170 - ns
= 19A, dISD/dt
= 100A/ µ s - 0.8 -
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD
= 25V, starting TJ
= 25oC,
L = 4mH, RG = 25Ω, peak IAS = 19A. (Figures 15, 16).
Typical Performance Curves Unless Otherwise Specified
POWER DISSIPATION MULTIPLIER
1.2
1.0
0.8
0.6
0.4
0.2
0
0
TC , CASE TEMPERATURE ( o 25 50 75 100 125 150 175
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
Z θJC, TRANSIENT
THERMAL IMPEDANCE ( o C/W)
1
0.1
0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
10-5 10-4 0.01
IRF9540, RF1S9540SM
©2002 Fairchild Semiconductor Corporation IRF9540, RF1S9540SM Rev. B
G
D
S
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
I D , DRAIN CURRENT (A)
-20
-20
-15
-10
-5
0
25 75 125
T C , CASE TEMPERATURE ( o C)
10
t1 , RECTANGULAR PULSE DURATION (s)
-3 10-2 10-1 1
P DM
t1 t2 NOTES:
DUTY FACTOR: D = t1 /t2 PEAK TJ = PDM x RθJC + TC µ C
10
175

Typical Performance Curves Unless Otherwise Specified (Continued)
I D , DRAIN CURRENT (A)
I D , DRAIN CURRENT (A)
200
100
rDS(ON), DRAIN TO SOURCE ON
RESISTANCE (Ω)
10
1
OPERATION IN THIS
AREA IS LIMITED
BY rDS(ON) 10µs
100µs
1ms
10ms
100ms
TC = 25
TJ = MAX RATED
SINGLE PULSE
0.1
1
10
100
VDS , DRAIN TO SOURCE VOLTAGE (V)
oC FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
-50
-40
-30
-20
-10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
DC
VGS = -5V
0
0 -2 -4 -6
VGS = -4V
-8
0.26
0.22
0.18
0.14
0.10
VGS = -16V
VGS = -14V
V GS = -10V
V GS = -9V
V GS = -8V
V GS = -7V
V GS = -6V
V DS , DRAIN TO SOURCE VOLTAGE (V)
V GS = -12V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V GS = -10V
500
0 -20 -40 -60 -80 -100
ID , DRAIN CURRENT (A)
IRF9540, RF1S9540SM
V GS = -20V
-10
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation IRF9540, RF1S9540SM Rev. B
I D , DRAIN CURRENT (A)
I DS(ON), DRAIN TO SOURCE CURRENT (A)
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
-100
-80
-60
-40
V GS = -16V
V GS = -14V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V GS = -12V
V GS = -10V
V GS = -9V
VGS = -8V
-20
VGS = -7V
0
0 -10
VGS = -6V
VGS = -5V
VGS = -4V
-20 -30 -40
-100
-10
-1
V DS , DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T J = 125 o C
T J = 25 o C
T J = -55 o C
-0.1
0 -2 -4 -6 -8 -10 -12 -14
VGS , GATE TO SOURCE VOLTAGE (V)
2.0
1.5
1.0
0.5
0.2
V GS = -10V, I D = 10A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
-50
-40 0 40 80 120 160
TJ , JUNCTION TEMPERATURE ( oC)

Typical Performance Curves Unless Otherwise Specified (Continued)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
g fs, TRANSCONDUCTANCE (S)
1.15
1.05
0.95
0.85
0.75
I D = 250µA
-40 0 40 80 120 160
T J , JUNCTION TEMPERATURE ( o C)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
15
12
9
6
3
0
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T J = -55 o C
T J = 25 o C
T J = 125 o C
-20 -40 -60 -80 -100
ID , DRAIN CURRENT (A)
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
V GS, GATE TO SOURCE (V)
0
- 5
-10
IRF9540, RF1S9540SM
VDS = -20V
VDS = -50V
VDS = -80V
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
©2002 Fairchild Semiconductor Corporation IRF9540, RF1S9540SM Rev. B
C, CAPACITANCE (pF)
I SD , SOURCE TO DRAIN CURRENT (A)
2000
1600
1200
800
400
100
10
C ISS
C OSS
C RSS
VGS = 0V, f = 1MHz
CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 0
0 -10 -20 -30 -40 -50
1
V DS , DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T J = 150 o C
0 20 40 60 80
Qg(TOT) , GATE CHARGE (nC)
T J = 25 o C
0.1
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
VSD , SOURCE TO DRAIN VOLTAGE (V)
I D = -19A

Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS 0V
VGS V GS
12V
BATTERY
0
t P
R G
V DS
I AS
0.01Ω
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
0.2µF
R G
50kΩ
I g(REF)
DUT
R L
CURRENT
REGULATOR
0.3µF
FIGURE 19. GATE CHARGE TEST CIRCUIT
G
L
DUT
-
VDD +
- VDD
IG CURRENT
SAMPLING
+VDS ID CURRENT
SAMPLING
RESISTOR RESISTOR
D
S
IRF9540, RF1S9540SM
+
-VDS (ISOLATED
SUPPLY)
DUT
DUT
FIGURE 20. GATE CHARGE WAVEFORMS
©2002 Fairchild Semiconductor Corporation IRF9540, RF1S9540SM Rev. B
0
0
0
V DS
VGS 0
V DD
0
V DD
t d(ON)
Q gs
I g(REF)
10%
t ON
50%
t r
I AS
90%
t P
10%
t AV
PULSE WIDTH
Q gd
Q g(TOT)
BV DSS
V DS
V DS
t OFF
t d(OFF)
V GS
90%
t f
90%
50%
10%

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This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
VCX
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
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This datasheet contains final specifications. Fairchild
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The datasheet is printed for reference information only.
Rev. H4