FOWLP & Embedded die Packages - I-Micronews

FOWLP & Embedded die Packages 

© 2012 

Embedded wafer-level-package activity is expected to pick-up by 2015 

above $200M overall driven by major wireless chip players worldwide 

Infineon 

STATs ChipPAC 

Nokia 

Texas 

Instruments 

AT&S 

Copyrights © Yole Développement SA. All rights reserved.

© 2012 • 2 

Table of Content (1/2) 

• Scope of the Report & Definitions …...……. 4 

• Executive Summary ………………………… 11 

1) Embedded die in substrates of active ICs & 

passive components ………………….……. 48 

– Motivations and Drivers ………………... 49 

– Application focus for Embedded die package 

commercialization …………………..…... 64 

• Cell-phone & Consumer applications 

• Automotive applications 

• Medical applications 

– 2010-2020 market forecasts for Embedded 

packages ………………………………….... 91 

• In Package shipments (M units) 

• In Packaging revenues ($M) 

– Supply chain emerging for embedded dies 

………………………………….…………….. 98 

• Players and position in the electronic value 

chain 

• Who is the most aggressive in 

commercialization? 

• Who is doing what: partnerships identified 

Copyrights © Yole Développement SA. All rights reserved. 

– Equt & Material Tool-Box for Embedded die . 129 

• Technology flavors for embedded package 

• Chip first versus chip last? 

• Single die embedding versus SiP module? 

• Challenges related to yield & supply chain 

– Cost structure for Embedded package 

manufacturing ………………………………….... 134 

• Comparison with competitive package alternative 

that Embedded die technology is looking for direct 

replacement (QFN, BGA, WLCSP, SOT, PoP…) 

• Cost structure target of Embedded die for different 

application cases (RFID, IPD, Power MOSFET / 

IGBT, DC/DC converters, PMU, Wireless 

Connectivity ICs, Digital Baseband, Memories, etc 

…) 

– Conclusion on “sweets spots” for the 

introduction of Embedded die technology in the 

short / medium / long term ……………………. 138 

FCI NXP

© 2012 • 3 

Table of Content (2/2) 

2) Fan-Out WLP technology development … 140 

– Motivations and market drivers …………... 144 

• Form factor, Cost and electrical performance 

• Thermal performance of FOWLP package 

compared to FC-BGA package solution 

– Supply chain emerging for FOWLP ……… 162 

• Players and position in the electronic value chain 

• Who is the most aggressive in commercialization? 

• Who is doing what: partnerships identified 

– 2010-2020 market forecasts for FOWLP type of 

packages ……………………………………... 174 

• In Package shipments (M units) 

• In epoxy wafer production (wspy eq.) 

• In Packaging revenues ($M) 

– FOWLP technologies & challenges …….. 202 

• Who owns the IP in this space? 

• 1 st generation versus 2 nd generation FOWLP 

• “Passive integration with FOWLP technologies 

– Equipment & Materials for FOWLP ............ 213 

• Challenges in new material selection and missing 

equipment 

• Technology roadmap for FOWLP development 

– 2.5D integration trends based on FOWLP and 

silicon / glass interposer mix ……….……. 227 


– FOWLP patent activity summary …... 233 

– Cost structure for FOWLP ………..…. 265 

• Competitive package alternative that FOWLP 

technology is looking for direct replacement 

• Cost structure for FOWLP by application 

– Evolution to Panel-scale-packaging .. 252 

• Conclusion & Perspectives ….………… 281 

• Appendix ……....…………….…..….…… 287 

– Yole Developpement company 

presentation & services 

StatsChipPAC

Wafer-Level 

Interface / Encapsulation 

LED & Sensors 

WLOptics 

© 2012 • 4 

3D WLP 

For MEMS & sensors 

(also called 3D SiP sometimes) 


Scope of the Report 

PANEL / Wafer-Scale-Packaging Platforms 

Wafer-Level 

Electrical Redistribution 

WL CSP 

‘Fan-in’ 

FOWLP 

‘Fan-out’ 

Embedded die 

in PCB / laminate 

� FOCUS of this report update 

Flip-chip & Wafer-Level 

Stacking / Integration 

3D IC 

& TSV 

Glass / Silicon 

2.5D 

interposers 

Flip-chip 

wafer bumping 

on BGA 

• Wafer-level-packaging encompass multiple different technology platform flavors 

but leverage similar type of process manufacturing know-how

© 2012 • 5 


Definitions 

• Embedded Packages refers to different concepts, IP, manufacturing infrastructures 

and related technologies. However, it is still possible to distinguish 2 main categories 

of embedded packages: 

Embedded 

Wafer-Level-Packages 

� based on a Molded Wafer infrastructure � based on a PCB / PWB substrate infrastructure 

NANIUM 

StatsChipPAC 

Wafer-Level Ball Grid Array 

eWLB 

Chip first 

UTCP 

Hidden die 

IMB 

EMBIDS / EDC 

Imbera 

Embedded Active Module 

iQFN 

ECP – Embedded Component Packaging 

EOMIN

© 2012 • 6 

Objectives of the Report 

• This is the second report update on Embedded Wafer-Level-Packaging 

technologies and markets from Yole Developpement 

• The objectives of this first report are the following: 

– Analyze both FOWLP and Embedded die package technologies 

– Key market drivers, benefits and challenges by application 

– Market trends & figures with detailed breakdown by application 

– Technology roadmap and description of the complete manufacturing tool-box 

for embedded wafer-level-packaging: 

o Key equipment: for 200mm / 300mm / Panel manufacturing 

o Specific material selection coming from both FE / BE / PCB / LCD areas 

– Analysis of several embedded package target prices for a few key applications 

– Supply chain perspectives, key players and emerging infrastructure for 

embedded wafer-level-packaging 

o Analysis of the rationales behind the different possibilities of FOWLP and embedded 

die package implementation (chip first / chip last, single die / multi-die / SiP / PoP 

module, etc …) 


© 2012 • 7 

Who should be Interested in this Report? 

• Integrated semiconductor Device 

Manufacturers and fabless IC companies 

– Benchmark the industrialization status of 

embedded packaging technologies within the 

industry 

– Identify possible partnerships or second 

source packaging subcontractors for your 

forthcoming developments 

• Assembly and Test Service companies 

– Get the list of the main companies interested 

in Embedded WLP 

– Screen possible new applications and 

technologies to support diversification 

strategy with embedded packaging platform 

• Equipment and Material suppliers 

– Understand the differentiated value of your 

products and technologies in this emerging 

but fast growing market 

– Identify new business opportunities and 

prospects 


• Electronic module makers and Original 

Equipment Makers 

– Evaluate the availability and benefits of using 

embedded package components in your end 

system 

– Monitor different embedded WLP suppliers 

to adjust your sourcing strategy 

• PCB and IC substrate manufacturers 

– Monitor the evolution of IC packaging, 

assembly and test, especially linked to 

emerging chip embedding 

– PCB-based technologies, FOWLP, IPD and 

3D interposers

© 2012 • 8 

Companies Cited in this Report 

3D-Plus, ADL Engineering, ADTEC Engineering, Amkor, ams, Analog 

Devices, AT&S, Aptos, Asahi Glass, ASE, ASM, Atotech, Broadcom, 

Bosch, Camtek, Casio Micronics, CIRETEC, CMK, Compass 

Technology, CSR, Datacon, Daeduck, Denso, Dialog Semiconductor, 

Dow Corning, DuPont Electronics, Dyconex, Epic, Epcos TDK, 

EVGroup, Fico Molding, Flip-chip International, Fraunhofer-IZM, 

Freescale, Fujitsu, HD Microsystems, HEICO, SK Hynix, Ibiden, 

Imbera, IME, IMEC, Infineon, Invensas, IPDiA, ITRI, King Dragon 

International, KYEC, Leti, Lintec, LG Electronic, Micron, MicroChem, 

Mitsui, Murata, Nagase ChemteX, NANIUM, NEC Electronics, Nitto 

Denko, Nokia, NSC, NXP, OptoPac Oki Electric, ORC, Panasonic, 

PPT, Qualcomm, Renesas, Rohm & Hass, Rudolph technologies, 

Samsung, SEMCO, Shinko Electric, SPIL, STATS ChipPAC, ST- 

Ericsson, STMicroelectronics, SPTS, SMIC, Shin-Etsu, SÜSS 

Microtec, Taiyo Yuden, TDK, Tessera, Texas Instruments, tok, Tong 

Hsing, Toray chemical, Toray Engineering, Toshiba, Towa, Triquint, 

UMTC, Unimicron, Unovis, UTAC, Vertical Circuits, Wolfson 

Microelectronics, Yamada and more… 


Jerome Baron 

© 2012 • 9 

About the authors of this report 

– Jerome is the business unit 

manager of the semiconductor 

packaging market research at 

Yole Developpement. He has 

been following the 3D packaging 

market evolution since its early 

beginnings at the device, 

equipment and material levels. 

He was granted a Master of 

Science degree from INSA-Lyon 

in France as well as a Master of 

Research from INL – Lyon 

Institute of Nanotechnology 

Contact: baron@yole.fr 


Lionel Cadix 

– Lionel joined Yole after the 

completion of several projects 

linked to the 

characterization and modeling of 

high density TSV and 3DIC chip 

stacking in collaboration 

with CEA-Leti and 

STMicroelectronics during his 

PhD. He is author of several 

publications and 8 patents in 

the field of 3D Integration 

Contact: cadix@yole.fr

Concepts of FOWLP / Embedded di in package 

• Two types of Embedded Wafer-level-packages are emerging 

© 2012 • 10 

– FOWLP is based on a reconfigured molded wafer infrastructure 

– Embedded die in package is based on a PCB type of Panel infrastructure 

FO MCP 


1 st generation 

NANIUM 

FO PoP 


AT&S 

FO SiP 

Embedded MCP 

Courtesy of AT&S 

Embedded PoP 


Single chip 

Embedded SiP

© 2012 • 11 

spacing 

Chip embedding 


Chip Embedding / Fan-Out WLP 

Geometry definitions 

width Line Spacing / Width (µm) 


Courtesy of NANIUM 

• Shift in manufacturing technologies is expected 

– Geometries of the two emerging packaging technologies will shrink with time as to allow for higher 

routing density, highly integrated passive inductors and baluns, and integration of ICs with no prior 

RDL on the device wafer 

– There is a move (at least for fan-out WLP) from currently used mask aligners to front-end steppers to 

support this reduction of the feature sizes 


1 st generation 

(up to 2012) 

2 nd generation 

(2012-2014) 

3 rd generation 

(2014-2020) 

40/40 25/25 15/15 

20/20 10/10 5/5

FOWLP / Embedded Die Packaging Roadmap 

SOT / TSOP 

© 2012 • 12 

MOSFET 

QFN 

IPD 

WL CSP 

RF connectivity, PMU, Analog 

FC BGA 

RF Transceiver, Baseband 

WB BGA 

PMU 



Micro-SiP module 

� RFID, thin-film IPD, MOSFET, 

IGBT, DC-DC converters, IC drivers, 

MEMS & Sensors , RFEM… 


FO MCP 

� Digital Baseband SOC 

� RF Transceiver 

� NFC / Connectivity SOC 

� ASIC / DSP / FPGA 

� Specific Analog IC & Sensors 

MATURE tech EMERGING tech FUTURE tech 

(2000 - 2010) (2008 - 2014) (> 2014 - 2018) 

Embedded MCP 

� Power modules, IPD 

protection network modules 

Digital / Analog partitioning … 

Embedded PoP 

� Digital + memory modules, 

Analog + Digital + memory 

modules, Sensor modules, 

Radio FEM module … 

FO PoP 

� Digital + memory modules, 

Analog + Digital + memory 

modules, Sensor modules … 

FO SiP 

� RF connectivity modules, 

Audio modules, Sensor 

modules, Radio modules …

© 2012 • 13 

Narrow commercialization window 

of present eWLB / FOWLP 1 st generation technology 

FO-MCP / SiP 

(for analog / digital SOC partitioning) 

• As of today (2012), the commercialization eWLB / FOWLP 1 st generation technology is quite 

restricted to a quite narrow application window from 40-300 IO pin-counts, 4x4 to 7x7mm2 

package body size 

– Package / devices below 4x4mm2 and 40 IOs: FOWLP will struggle to compete with Wire-bonded 

BGA/leadframe, Embedded die package and 3DIC wafer-to-wafer assembly platform � An extra niche to be 

found by developing FO-MCP / SiP platform here 

– Package / devices of more than 15x15mm²: flip-chip and 2.5D interposer are the best packaging solutions 

today � new flip-chip and 2.5D version of FOWLP technology will be adapted to compete on cost 

– Between 4x4mm2 and 15x15mm²: the solutions are not yet decided and the battle is hard between most 

every packaging technique � and this is where the biggest part of the IC packaging business is in volume! 



(commercialized TODAY) 

FO-PoP (for BB/APE) 

2.5D FOWLP 

(for APE / ASIC + memory + analog) 

Flip-chip FOWLP 

(for large die ASIC / FPGA) 

4 – 10 IOs 10 – 40 IOs 40 – 300 IOs 300 – 700 IOs 700 – 1000’s IOs 

I/O# 

numbers 

2x2 mm2 4x4 mm2 7x7 mm2 

15x15 mm2 25x25 mm2 package 


3DIC (W2W) FC-CSP / BGA 

2.5D interposers (C2W) 

body size 

WB BGA / 

QFN / TSOP 

Logic n Logic n+1 Logic n+2 Logic n+3

FC BGA 

Embedded 

die in PCB 

© 2012 • 14 

Packaging Value Chain Comparison* 

Comparison ratio of the packaging, assembly & test value 

Substrate Supplier 


Substrate Supplier 

& Assembly 


Inventory 

Wafer Fab 

(RDL) 

Wafer 

Bumping 

Wafer Fab + FOWLP 

assembly 

Assembly & Test 

20% 25% 10% 45% 

Wafer 

Test + 

Final 

Test 

85% 15% 

Wafer Fab 

(RDL & Cu pad) 

Wafer Test 

+ Final 

Test 

55% 30% 15% 

• New shift in the packaging, assembly & test value chains 

* Comparison 

scenario for the 

case of 64 I/Os, 

0.4mm pitch IC 

PRODUCT 

PRODUCT 

PRODUCT 

– FOWLP implies a simplification and consolidation of the packaging, assembly & test in a “Mid-end” 

type of infrastructure 

– Embedded die packaging opens the door to substrate suppliers to realize themselves the whole 

packaging, assembly and test on a Panel “PCB based” infrastructure

Package IC Co-Design is Necessary Before Embedded WLP 

© 2012 • 15 

SERIAL IC Design Package IC Co-Design 

Digital IC design 

Tool A 

Tool B 

Analog IC design 

Tool C 

Tool D 

Manufacturing 

PRODUCT 

Packaging design 

Substrate 

Package outline 

FE/BE process 


FE / BE Manufacturing 

Analog IC 

design 

Packaging 

development 

PRODUCT 

Digital IC 

design 

DfM � Designed for manufacturing 

Infrastructure � Common Tool-Box 

• Package IC co-design drives to silicon die and process optimization, for e.g. 

– to avoid RDL at the IC wafer level before the embedded WLP process 

– RF chip package co-design is also necessary to integrate to take package parasitics into accounts

Embedded die in 

package 

(Single chip modules) 

X 

© 2012 • 16 

X 

Casio / CMK – Watch module 

Embedded Wafer-Level-Packages 

Status of commercialization 


1 st generation / single die 

X Broadcom – ASIC 

StatsChipPAC 

X Altera – FPGA 

X STEricsson – RF Transceivers 

X IFX / Intel Mobile – Wireless Baseband SOC 

X Maxim IC – PMU 

X SST – EEPROM memories 

X Renesas – ASIC X Toshiba – FPGA 

Murata – Cellular terrestrial digital module 



SiP / PoP module 

packages 

2 nd generation 


X TI – DC/DC converter 

NXP – RFID / IPD modules 

2006 2007 2008 2009 2010 2012 2014 2016 2018 

X 

X 

FO SiP 

X 

X 

ADI 

X 

X Infineon 

X ams 

X 

X 

FO MCP 

FO PoP 

Embedded SiP Embedded PoP 

Rohm – DC/DC converter 

X 

X 

X 

X 

X 

X

First eWLB Package in High Volume Production! 

• First design win for eWLB 

© 2012 • 17 

– Infineon (GE) was the first company 

to commercialize its own eWLB 

packaging technology in an LGE 

cell-phone in early 2009 

– ASE, StatsChipPAC have been 

qualified as subcontractors 

for eWLB manufacturing 

– Infineon’s chip is a wireless 

baseband SOC 

with multiple 

integrated functions 

(GPS, FM radio, BT…) 

– Same eWLB 

product is now in 

production in 

some Nokia 

handsets 

since 2010 


First eWLB 

package with 

Infineon’s 

wireless 

Baseband SOC 

was found in 

an LG cellphone 

(Reverse 

Engineering 

pictures courtesy 

of SystemPlus 

Consulting and 

Binghamton 

University )

Current end-products using eWLB / FOWLP 

• Mobile and wireless applications using FO-WLP packaging 

© 2012 • 18 

– LGE was the first OEM to integrate the eWLB to the wireless baseband in the following models 

• PMB8810 phone, T310 phone, T300 phone, GD350 phone, GB220 phone, GB230 phone, GS170 phone, GU230 phones 

– We can also find eWLB in Samsung cell phones (baseband modem) 

• S3350 phone, Galaxy Tab tablet, Galaxy S phones 

– Some Nokia’s phones use eWLB for the baseband modem and RF tranceiver 

• S30 series platform (2010 phone version), S40 series platform (2010 phone version), 1 smart-phone line (to be identified) 

2009 2010 2011 

• Extension of the technology platform to a wider field of application areas is in 

preparation 

– FO-WLP is expected to be integrated as well as some point in the automotive and medical 

applications 


FO-WLP Revenues (M $) 

$0M 

2008 2009 2010 2011 2012F 2013F 2014F 2015F 2016F 2017F 2018F 2019F 2020F 

TOT FOWLP (M$) $13M $48M $75M $107M $114M $107M $118M $195M $280M $374M $477M $571M $641M 

© 2012 • 19 

FOWLP activity market evolution & forecast 

$700M 

$600M 

$500M 

$400M 

$300M 

$200M 

$100M 

Copyrights © Yole Developpement SA. All rights reserved. 

FOWLP activity Revenues (M$) 

Overall evolution since eWLB technology introduction 

Yole Developpement © October 2012 

Intel Mobile / 

IFX eWLB driven 

Transition phase 

CAGR ~ 0% 

Ramp-up with fab-less wireless 

IC players and wide FOWLP 

infrastructure / supply-chain 

• After growing fast since Infineon / Intel Mobile’s push for eWLB technology commercialization, the FOWLP 

market activity reached the $100M market valuation last year 

– This young industry will probably need to wait for 2015 – 2016 time frame to reach the $250M market valuation as the technology 

to ramp-up in HVM, the demand moving from IDMs to fab-less wireless IC players (such as Qualcomm, Broadcom, Mediatek, 

etc…) and supported by a solid infrastructure and supply-chain of OSATs

© 2012 • 20 

Optimistic scenario (1/2) 

• To bend the rules, we decided in this report to propose an alternative scenario for FOWLP 

market evolution 

• Indeed, regarding the numerous rumors linked to this space, several feedbacks pushed us 

to propose an optimistic forecast model, making the market starting growing fast as soon as 

2013 

• This enthousiastic scenario would be linked to the following players’ activity 

– Spreadtrum (CN) 

– Maxim (US) 

– ADL (TW) 

– Mediatek (TW) 

• In this alternative model 

– A 30% penetration rate have been 

applied for FOWLP as soon as 

2013, for existing products already 

using this platform 

• Digital Baseband Processor 

• APE/BB wireless SoC 

– Volume production for the other 

applications would start 1 year 

sooner than in our initial model (for 

RF tranceiver, PMU, ASIC, 

Touchscreen Controller, RF 

Connectivity devices) 


FO-WLP Revenues (M $) 

1 200 

1 000 

800 

600 

400 

200 

0 

FOWLP Revenues (optimistic scenario) 

Breakdown by application area (M$) 

Yole Developpement © October 2012 

2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 

Medical 

Automotive 

Industrial 

Consumer 

Mobile - Wireless

Wafer count (12’’eq. wafers) Millions 

3.0 

2.5 

2.0 

1.5 

1.0 

0.5 

0.0 

© 2012 • 21 

Optimistic scenario (2/2) 

Yole Developement © October 2012 

2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 


FOWLP wafer forecast (optimistic scenario) 

Breakdown by IC type (12’’eq wafers) 

DRAM 

Touchscreen Controller 

RF Connectivity Combo 

PMU 

NAND Flash Memory 

Memory Controller 

MEMS & Sensors 

NFC 

RF Tranceiver 

ASIC / FPGA 

Audio/Video Codec 

Digital Baseband Processor 

BB/APE wireless SoC 

• According to this model the market would grow at a 30% CAGR on the 2010-2020 time frame, 

leading to a ~ $1B market in 2020 

• It would lead to nearly 500,000 wafers shipped in 2020 and more than 2.8 billion in 2020 

• Now we just have to wait and see if the rumors come true and if the infrastructure of this 

young industry will be strong enough to support this fast growing evolution

FOWLP 2011 revenues market shares (in M$) 

© 2012 • 22 

FOWLP 2011 revenues market shares (in M$) 

Breakdown between main players 

ASE (Tw) 

$14M 

13% 

NANIUM (Pt) 

$41M 

38% 

• NANIUM (Pt) and STATschipPAC (Sg) shares more than 80% of the activity, mainly driven by 

Intel Mobile volume demand on eWLB production 

– ASE (Tw) is shutting down its 200mm eWLB line. Other OSATs have qualified other FOWLP technologies 

such as ADL (Tw), Amkor (Kr) and NEPES (Sg) 

– Additional packaging houses are coming on board as well such as TSMC (Tw), SPIL (Tw) and J-Devices (Jp) 


Others * 

$6M 

6% 

TOT 

~$107M 

* Others: ADL (Tw), 

Amkor (Kr), NEPES (Sg) 

STATSChipPAC (Sg) 

$46M 

43% 

Yole Developpement © 

October 2012

PANEL Infrastructure for Embedded Chip Packaging 

• Embedded die packaging technology will leverage an entirely new infrastructure 

based on large PANEL, low cost PCB manufacturing techniques! 

© 2012 • 23 

– Typically able to integrate more than 10,000 – 40,000 dies per panel! 



� AT&S’s first generation production is based on 18x24 sq. 

inch panels. 2 nd gen on 21x24 sq. inch panels!

AT&S step into HVM for Embedded MicroSiP packages 

• Texas Instruments (US) is the first customer to qualify into HVM 

the embedded die package line of AT&S 

– First application is a DC-DC converter MicroSiP module: 

Teardowns courtesy of SystemPlus Consulting 

© 2012 • 24 

Copyrights © Yole Developpement SA. All rights reserved.

DNP’s Embedded active & passive substrate in HVM 

• DNP (JP) is supplying Sony’s camera module with embededded passive and active 

components in HVM since 2010 already 

– Auto-focus driver IC and DC-DC converter WLCSP dies are placed within the coreless cavity substrate 

© 2012 • 25 


Teardowns courtesy of SystemPlus Consulting

Embedded die package PANEL infrastructure Roadmap 

Substrate 

players driven 

2010 - 2012 2013 2014 2015 > 2016 

© 2012 • 26 

OSAT 

players driven 

4”x20” – 102x508mm / 

PCB laminate substrate 

1/4 PANEL 


YIELD % to increase 

POWER & ANALOG 

small SiP module applications: 

- DC/DC converter 

- IPD 

- AF driver 

- Small ASICs 

- MOSFET 

- IGBT 

- RFID 

8”x20” – 204x508mm / 


1/2 PANEL 

DIGITAL 

thin PoP module applications 

- BB / APE 



16”x20” – 400x505mm / 


RF & MIXED SIGNAL 

large SiP module applications : 

- PMU / PMIC 

- RFEM (SAW, PA, etc…) 

- RF connectivity (WLAN/BT/FM) 

- Audio/Video Codec 

Full 

PANEL 

RF & MIXED SIGNAL 

SiP module applications : 

- PMU / PMIC 

- RFEM 

- RF connectivity (WLAN/BT/FM) 

- Audio/Video Codec

© 2012 • 27 

First Conclusions on Embedded Wafer-Level-Packages 

• 1st generation FOWLP and Embedded die packages is a high volume reality and the two 

infrastructures are now clearly settled and proven in HVM in each of their very different 

application space 

– Today, first generations of Embedded die package and FOWLP technologies are not really competing 

at all as they are driven by different players and initially target very different applications. 

• However, this situation will totally change in the future with “2nd generation” derivatives of 

the technologies that are currently under development for future SiP and PoP module 

realizations, likely on larger format 

– We are likely to be witness to a fascinating battle in the years to come in the 3D Packaging space with 

on one hand, embedded die packaging technologies supported by large panel PCB infrastructure and 

FOWLP technologies on the other hand, which is looking for moving to larger wafer format, likely 

square 300mm PANEL first and possibly later on larger PANEL mixing PCB, semiconductor backend, 

semiconductor WLP and LCD large area processing know-how 


© 2012 • 28 


Yole Developpement 

Company Presentation

© 2012 • 29 

Fields of research activity 

• Yole Developpement is a market research and strategy consulting 

company, founded in 1998. We are involved in the following areas: 

Advanced 

Packaging 

Microfluidic 

& Bio-tech 

LED & 

Compound Semi 

• Yole Développement has 25 full time analysts, with both technical and 

marketing/management background and operate worldwide since 1998 


MEMS & 

Sensors 

Power 

Electronics 

Photovoltaic

© 2012 • 30 

Our Global Presence & Activity 

30% of our activity is 

in North America 

Yole Inc. 

� perkins@yole.fr 


40% of our activity is in 

EU Countries 

Yole Europe 

� eloy@yole.fr 

Yole Développement 

Lyon (HQ). 

Yole Korea 

� yang@yole.fr 

30% of our activity is 

in Asia 

Yole Japan 

Yole Taiwan 

� katano@yole.fr 

� meiling.tsai@yole.com.tw

© 2009 

HB-LED LED Packaging 

Market Technology & Technology & Market Trends 

Osram 

IR 

Copyrights © Yole Développement SARL. All rights reserved. 

TSV+ 

Cost Analysis Tool for 

your 3D IC manufacturing 

© 2012 • 31 

TSV Scenario Cost structure breakdown 

$168 

41% 

1995 

Sidebraze DIP 

$27 

7% $23 

6% 

$8 

$31 

$9 $37 2% 

7% 

2% 9% 

$109 

26% 

Via / Etching Drilling 

Via Isolation 

Via filling 

Temporary bonding 

Thinning 

Stress release 

BEOL (Pads) 

Bonding 

© 2010 

~125 sq mm ~100 sq mm ~25 sq mm 

1996-2002 

1999 - today 2006 

Plastic PDIP 

FO WLP & 


Our latest advanced packaging 

market research reports 

SMT SOIC 

& Die Down 

MEMS Packaging 

Market & Technology Trends 

Stacked Die 

QFN 

6 & 6 mm 

WL CSP 

2012 Report update 


1995 

Sidebraze DIP 


~125 sq mm ~100 sq mm ~25 sq mm 

1996-2002 

1999 - today 2006 

Plastic PDIP 

Wafer Packaging Fabs 

DATABASE 

N 

o 

k 

i 

a 

SMT SOIC 

& Die Down 

N 

o 

k 

i 

a 

3D IC & TSV 

2010 Market Analysis 

F 

r 

e 

s 

c 

a 

l 

e 

Stacked Die 

QFN 

6 & 6 mm 

2.5D Glass & Silicon 

interposers - 2010 Report 

© 2010 

Equipment Advanced Packaging 

& Materials 

for 3DIC & Wafer-Level-Packaging 

EVG 

Equipment & Materials 

S 

i 

l 

e 

x 

D 

u 

P 

o 

n 

t 

DuPont 

NEC-Schott 

SUSS STS 

Brewer Science 

I 

M 

E 

C 

Copyrights © Yole Développement SARL. All rights reserved. 

N 

o 

k 

i 

a 

Via First / Via Last? 

3D integration Scenarios 

F 

r 

e 

s 

c 

a 

l 

e 

IPD - Thin-film 

Integrated Passive Devices 

S 

i 

l 

e 

x 

D 

u 

P 

o 

n 

t 

Flip-chip 

2011 Report 

I 

M 

E 

C

© 2012 • 32 


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