pdf-Katalog - IMMS Institut für Mikroelektronik
pdf-Katalog - IMMS Institut für Mikroelektronik
pdf-Katalog - IMMS Institut für Mikroelektronik
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Tasks<br />
• Become familiar with mixed-signal circuit simulation using Cadence AMS Designer<br />
• Become familiar with the verification language SystemVerilog and the Universal Verification<br />
Methodology (UVM)<br />
• Create a UVM-based virtual test environment for an RFID sensor tag<br />
• Implement and simulate a set of application and error scenarios for the test environment<br />
Prerequisites<br />
• Object-oriented programming skills<br />
• Knowledge of digital hardware description languages (Verilog or VHDL)<br />
Desirable experience<br />
• Analog and/or digital IC design and simulation with Cadence design tools<br />
• SystemVerilog<br />
• Universal Verification Methodology (UVM)<br />
Type & Period<br />
• Internship (6 months), also possible as Master’s Thesis<br />
Studentenangebote <strong>IMMS</strong> 2012/2013 15
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