Indy R1000 Datasheet - Impinj

Indy R1000 ® Electrical, Mechanical, & Thermal Specification
5 Functional Description
The transmitter supports both in-phase quadrature (I-Q) vector modulation and polar modulation. The direct IQ up-conversion is intended for single
sideband amplitude shift keying (SSB-ASK) and phase reversal amplitude shift keying (PR-ASK). The polar modulation is intended for double
sideband amplitude shift keying (DSB-ASK). In both cases, the signals are generated in the digital domain and converted to analog signals by sigmadelta
digital-to-analog converters followed by reconstruction filters. The integrated PA can be operated in three different modes:
• Class F with high output power and without internal amplitude modulation (AM)
The PA acts as a driver for an external PA. The AM is performed in the external PA, but it does require an external modulator.
• Class A required for SSB-ASK and PR-ASK
An optional linear external PA can be fitted to increase the output power to the maximum allowed level.
The baseband encoding and pulse-shaping is done with a lookup table to minimize latency. In the case of SSB-ASK transmission, the baseband
signal is filtered with a Hilbert filter to create a complex IQ signal with suppressed negative frequencies. The signal is then offset in frequency to
center the SSB-ASK spectrum in the channel. The digital I and Q signals are converted into the analog domain by sigma-delta DACs.
In DSB-ASK transmission, the baseband encoding and pulse shaping is performed in the same manner as it was for SSB-ASK, but the shaped signal
is pre-distorted to compensate for non-linearity in the AM transfer function. The pre-distorted AM control signal is converted into the analog domain
by the I and Q sigma-delta DACs as defined in the lookup tables.
The receiver is in principle a homodyne to ensure that as much as possible of the transmitter (TX) leakage falls on DC. The receiver downconversion
mixer can be driven either by the internal local oscillator (LO) signal or by an external LO signal typically tapped off from the output of the external
PA. The receiver uses a single on chip low noise amplifier (LNA). If the system needs to accommodate a +10-dBm jammer, a 4-dB external
attenuator is required.
After downconversion, the major part of the DC is removed by resettable AC-coupling capacitors. The analog intermediate frequency (IF) filter
provides coarse channel selectivity. It has programmable bandwidth to accommodate for the large range of required data rates. The coarsely filtered I
and Q signals are analog-to-digital converted. Automatic IF gain stepping in the filter reduces the required dynamic range of the ADC. Sharp and
well controlled digital filtering supplements the coarse analog filtering. The demodulation is also performed digitally.
The clocks for the digital blocks are derived from a 24-MHz reference frequency originating from an external temperature compensated crystal
oscillator (TCXO). The sigma-delta DACs run directly on the 24-MHz signal. The sigma-delta ADCs run on a 48-MHz clock generated by an
integrated frequency doubler.
The VCO is fully integrated. The loop filter is external for the synthesizer to meet the stringent phase noise requirements. The time reference
required by the phase locked loop (PLL) and the digital blocks is derived from the 24-MHz reference frequency.
The Indy R1000 reader chip supports two interfaces, one low speed parallel interface with a data rate of up to 20 Mbps, and one serial interface with
a data rate of 150 Mbps to the Indy R1000 reader chip and up to 450 Mbps from the Indy R1000 reader chip. The interfaces are multiplexed on the
same pins, and the interface is determined during power-up. Both interfaces are operated at 3.3 V. Low level instructions are written into a first in,
first out (FIFO) buffer and executed one at a time by the Indy R1000 reader chip. All information is transferred via the register bank. The control of
the Indy R1000 reader chip is state machine driven.
14 Revision 2.3, Copyright © 2012, Impinj, Inc.