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F4: Ultra-Low-Voltage Circuit Design
FORUMS
Organizer: Rajeevan Amirtharajah, University of California, Davis, CA
Committee: Tzi-Dar Chiueh, National Taiwan University, Taipei, Taiwan
Ram Krishnamurthy, Intel, Hillsboro, OR
Jos Huisken, IMEC, Eindhoven, Netherlands
Siva Narendra, Tyfone, Portland, OR
Steffen Paul, Universität Bremen, Bremen, Germany
Pascal Urard, STMicroelectronics, Crolles, France
Alice Wang, Texas Instruments, Dallas, TX
Low-power CMOS design has relied heavily on VDD scaling, in the past, to exploit the
quadratic dependence of dynamic power and the exponential dependence of leakage
power on voltage. Today, leading-edge low-voltage designs are pushing FET operation
into the weak inversion and subthreshold regimes. Investigators around the world are
reporting circuits at voltages between 180mV and 700mV that offer performance that
could support a range of applications in wireless sensors, mobile phones, biomedical
devices, and ultra-mobile PC's. However, these circuits are highly sensitive to variations
in temperature and process. Ultra-low-voltage circuits will be increasingly challenging to
design as feature sizes shrink. Current trends indicate nominal supply voltages are
unlikely to be reduced much below 1V, transistor threshold voltages will likely remain
between 0.3 and 0.4V to manage subthreshold leakage, and effects such as random
dopant fluctuation will increase the spread in transistor parameters, all of which create
difficulties in designing robust circuits at low VDD. This forum brings together leading
experts to describe future challenges in ultra-low-voltage design, to explore ultra-lowvoltage
circuit techniques, and to stimulate thinking about prospects for future ultralow-voltage
high-volume products.
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