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Download PDF - International Solid-State Circuits Conference

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SESSION 2<br />

IMAGERS<br />

Session Chair: Jan Bosiers, DALSA Professional Imaging, Eindhoven, Netherlands<br />

Associate Chair: Makoto Ikeda, University of Tokyo, Tokyo, Japan<br />

2.1 A 4-Side Tileable Back-Illuminated 3D-Integrated Mpixel CMOS Image Sensor<br />

1:30 PM<br />

1 1 2 1 1 1 1<br />

V. Suntharalingam , R. Berger , S. Clark , J. Knecht , A. Messier , K. Newcomb , D. Rathman ,<br />

1 1 1 1 1 3 3<br />

R. Slattery , A. Soares , C. Stevenson , K. Warner , D. Young , L. Ang , B. Mansoorian ,<br />

1 D. Shaver<br />

1MIT Lincoln Laboratory, Lexington, MA<br />

2Irvine Sensors, Costa Mesa, CA<br />

3Forza Silicon, Pasadena, CA<br />

A 3D-integrated back-illuminated 1Mpixel CMOS image sensor tile includes a stack of<br />

2×32-channel vertically integrated ADC chips, and requires 13.4μm of silicon perimeter to the<br />

pixel array. The tile and system connector design supports 4-side abuttability and burst data<br />

rates of 1Mpixel in 1ms.<br />

2.2 A Gamma, X-Ray and High-Energy-Proton Radiation-Tolerant CIS for Space<br />

Applications<br />

2:00 PM<br />

1 1 1 1 1,2<br />

L. Carrara , C. Niclass , N. Scheidegger , H. Shea , E. Charbon<br />

1EPFL, Lausanne, Switzerland<br />

2Delft University of Technology, Delft, Netherlands<br />

This paper presents a 0.35μm CIS that is tolerant to gamma, X-ray and 11MeV/60MeV proton<br />

radiation. Its core is an array of 32×32 pixels each containing a static memory and a<br />

single-photon detector. A 2-gray-level frame is transfered in 1.2μs. The chip tolerates 1Mrad of<br />

gamma, 40krad of proton, and 1mGy of X-ray radiation. The dark-count-rate degradation is<br />

contained or negligible.<br />

2.3 A 4-Channel 20-to-300Mpixel/s Analog Front-End with Sampled Thermal Noise Below<br />

kT/C for Digital SLR Cameras<br />

2:30 PM<br />

1 2 3 3 2 1 1<br />

R. Kapusta , E. Ibaragi , K. Ni , R. Wang , H. Shinozaki , L. Singer , K. Nakamura<br />

1Analog Devices, Wilmington, MA<br />

2Analog Devices, Tokyo, Japan<br />

3Analog Devices, Beijing, China<br />

A 0.18μm CMOS 4-channel AFE for digital SLR cameras is reported that is optimized for clock<br />

rates of 5 to 75MS/s/channel and that uses nonlinear adaptive biasing based on clock<br />

frequency. Optimization techniques for a multi-channel system achieve -85dB crosstalk and<br />

0.01% channel mismatch. Sub-kT/C sampling achieves 80dB DR and uses capacitors that are<br />

60% smaller than normal.<br />

Break 3:00 PM<br />

18

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