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DISPLAY AND IMAGER ELECTRONICS Session Chair: Iliana Fujimori-Chen, Analog Devices, Wilmington, MA Associate Chair: Oh-Kyong Kwon, Hanyang University, Seoul, Korea 15.1 A Piecewise-Linear 10b DAC Architecture with Drain-Current Modulation for Compact AMLCD Driver ICs 1 1 1 1 2 2 2 Y-J. Jeon , H-M. Lee , S-W. Lee , G-H. Cho , H. Kim , Y-K. Choi , M. Lee 1 2 KAIST, Daejeon, Korea; Samsung Electronics, Yongin, Korea 1:30 PM A piecewise-linear 10b DAC for an AMLCD data driver with interpolation by drain-current modulation is reported. The DAC achieves a DNL of 0.37 LSB and INL of 1.71 LSB. Output voltage mean and standard deviation of 6.35mV and 0.54mV are achieved. Each DAC occupies 14×473μm 2 in 0.10μm CMOS and total chip power consumption is 9.4mW. 15.2 A 10b Column Driver with Variable-Current-Control Interpolation for Mobile Active-Matrix LCDs 1 1 1 1 2 2 2 H-M. Lee , Y-J. Jeon , S-W. Lee , G-H. Cho , H-R. Kim , Y-K. Choi , M. Lee , 1KAIST, Daejeon, Korea 2 Samsung Electronics, Yongin, Korea SESSIONS 15 & 16 2:00 PM A 10b column driver for mobile AMLCDs uses variable-current-control interpolation in buffer amplifiers. Bias-current steering improves the interpolation accuracy. The INL and DNL are 0.7 LSB and 0.4 LSB, respectively. A total chip size of 20.18×1.68mm 2 is obtained in a 0.10μm 1.5V/5V CMOS process. The total power consumption is 20mW. 15.3 A 0.1e - Vertical FPN 4.7e - Read Noise 71dB DR CMOS Image Sensor with 13b Column-Parallel Single-Ended Cyclic ADCs 2:15 PM 1 1 1 1 1 1 1 1 J. Park , S. Aoyama , T. Watanabe , T. Akahori , T. Kosugi , K. Isobe , Y. Kaneko , Z. Liu , 1 1 2 K. Muramatsu , T. Matsuyama , S. Kawahito 1 2 Brookman Lab, Hamamatsu, Japan; Shizuoka University, Hamamatsu, Japan A CIS with 13b column-parallel cyclic ADCs is presented. A single-ended architecture with low read noise increases DR up to 71dB. A vertical FPN of 0.1e - rms is attained using digital CDS, which performs A/D conversion twice in a horizontal scan period of 6.83μs. The imager has 7.07V/lx·s sensitivity, 5.6μm ADC pitch, 61μV/e - conversion gain, 4.7e - rms read noise and
Tuesday, February 10th 1:30 PM HIGH-SPEED AND mm-WAVE CIRCUITS Session Chair: Kumar Lakshmikumar, Conexant Systems, Red Bank, NJ Associate Chair: Jae-Yoon Sim, Pohang University of Science and Technology, Pohang, Korea 16.1 An 18Gb/s Duobinary Receiver with a CDR-Assisted DFE K. Sunaga, H. Sugita, K. Yamaguchi, K. Suzuki NEC, Sagamihara, Japan 3:15 PM A 90nm CMOS DFE achieves 18Gb/s over 25cm low-ε PCB trace. Binary signals from the transmitter are equalized to duobinary waveforms. The ISI is suppressed without the need for DFE tap feedback within a symbol interval. The symbol-rate CDR generates accurate sampling clocks for both data and edge. The overall circuit area is 480×420μm 2 , and the receiver consumes 100.2mW from a 1.2V supply when operating at 18Gb/s. 16.2 A 43.7mW 96GHz PLL in 65nm CMOS K-H. Tsai, S-I. Liu National Taiwan University, Taipei, Taiwan 3:45 PM A 96GHz PLL is fabricated in a 65nm CMOS process. The VCO circuit is designed by optimizing active and passive devices to achieve a low power consumption of 43.7mW from a 1.2V supply. The PLL locks from 95.1 to 96.5GHz. The reference spur is less than -50dBc. 16.3 An Array of 4 Complementary LC-VCOs with 51.4% W-Band Coverage in 32nm SOI CMOS 4:15 PM 1 2 1 3 1 1 1 D. Kim , J. Kim , C. Cho , J-O. Plouchart , M. Kumar , W-H. Lee , K. Rim 1 2 IBM, Hopewell Junction, NY; Qualcomm, San Diego, CA 3IBM T. J. Watson, Yorktown Heights, NY An array of 4 complementary LC-VCOs is implemented in 32nm SOI CMOS technology for wide-band tuning. The VCOs tune from 83.2 to 96.7GHz and from 100.1 to 104.3GHz, covering 51.4% of W-band. The VCOs occupy 40×35μm2 and are scalable for an array implementation in nanometer SoC. The array of parallel VCOs aims to overcome process variation and to improve yield. 16.4 A mm-Wave CMOS Multimode Frequency Divider 4:30 PM 1 2 3 3 1 1 H-K. Chen , H-J. Chen , D-C. Chang , Y-Z. Juang , Y-C. Yang , S-S. Lu 1 2 National Taiwan Univeristy, Taipei, Taiwan; Faraday Technology, Hsinchu, Taiwan 3Chip Implementation Center, Hsinchu, Taiwan A multiband multi-mode ILFD operates at 38 and 57GHz. A conventional divide-by-2 ILFD is extended to include the function of divide-by-3. The chip is implemented in a 0.13μm CMOS and consumes 3.12mW from a 1V supply. The core occupies 0.023mm2 . 16.5 A 128.24-to-137.00GHz Injection-Locked Frequency Divider in 65nm CMOS 4:45 PM B-Y. Lin, K-H. Tsai, S-I. Liu National Taiwan Univeristy, Taipei, Taiwan A 65nm CMOS ILFD uses split injection and split cross-coupled pair and has a locking range of 128.24 to 137.00GHz. It consumes 5.5mW from a 1.1V supply excluding the biasing circuit and buffers. The core area is 0.32×0.16mm2 . Conclusion 5:00 PM 49
Page 1 and 2: IEEE SOLID-STATE CIRCUITS SOCIETY A
Page 3 and 4: CONFERENCE INFORMATION Tutorials ..
Page 5 and 6: Sunday, February 8th T1: Continuous
Page 7 and 8: Sunday, February 8th Instructor: An
Page 9 and 10: F1: SSD Memory Subsystem Innovation
Page 11 and 12: F2: Medical Image Sensors Organizer
Page 13 and 14: Time Topic 8:00 Breakfast Forum Age
Page 17 and 18: Monday, February 9th 8:15 AM PLENAR
Page 19 and 20: Monday, February 9th 8:15 AM Adapti
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Page 23 and 24: Monday, February 9th 1:30 PM 3.5 Se
Page 29 and 30: Monday, February 9th 1:30 PM 6.4 Si
Page 31 and 32: SE4: Highlights of IEDM 2008 Organi
Page 33 and 34: SE5: Things All RFIC Designers Shou
Page 35 and 36: Tuesday, February 10th 8:30 AM 7.5
Page 39 and 40: 9.5 A 0.13μm CMOS 78dB SNDR 87mW 2
Page 47 and 48: Tuesday, February 10th 1:30 PM 13.4
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Page 55 and 56: RANGING AND Gb/s COMMUNICATION Sess
Page 57 and 58: SESSION 19 ANALOG TECHNIQUES Sessio
Page 59 and 60: SE6: Interleaving ADCs - Exploiting
Page 61 and 62: SESSION 20 SENSORS AND MEMS Session
Page 63 and 64: SESSION 21 10Gb/s-to-40Gb/s TRANSMI
Page 65 and 66: PA AND ANTENNA INTERFACE Session Ch
Page 67 and 68: SESSION 23 PLLs AND CLOCKs Session
Page 69 and 70: SESSION 24 WIRELESS CONNECTIVITY Se
Page 71 and 72: SESSION 25 MEDICAL Session Chair: A
Page 73 and 74: SWITCHED-MODE TECHNIQUES Session Ch
Page 75 and 76: SESSION 27 SRAM AND EMERGING MEMORY
Page 77 and 78: SESSION 28 TD: DIRECTIONS IN COMPUT
Page 79 and 80: mm-WAVE CIRCUITS Session Chair: Fra
Page 81 and 82: SHORT COURSE Low-Voltage Analog and
Page 83 and 84: SHORT COURSE The Effect of Technolo
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Page 93 and 94: INFORMATION • Local Chapter meeti
Page 95 and 96: INFORMATION other women in the prof
Page 97 and 98: COMMITTEES INTERNATIONAL TECHNICAL
Page 99 and 100: COMMITTEES MEMORY SUBCOMMITTEE (con
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EUROPEAN REGIONAL COMMITTEE ITPC EU
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FAR-EAST REGIONAL COMMITTEE (contin
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CONFERENCE SPACE LAYOUT The Confere
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