Download PDF - International Solid-State Circuits Conference

SESSION 1
Another problem in the nanoscale era, that is, the ever-higher interconnect resistance, is
also closely related to the voltage-limitation problem at the chip and subsystem levels: It
further increases the actual operating voltage, since, while it degrades the speed of everlarger
chips, it reduces power-supply integrity by increasing power-supply droop and
noise in power-supply lines. For the ULSI industry to continue to proliferate, the voltagescaling-limitation
problem must be solved in the 32-nm generation and beyond. This
requires a multidisciplinary approach, since it covers various fields, such as, devices,
circuits (digital and analog), and subsystems.
This Plenary talk will address issues related to adaptive circuits and relevant
technologies intended to reduce Vmin and ensure power-supply integrity. Vmin reduction
is described in the first half. After comparing Vmin values for several blocks, namely,
logic, SRAM and DRAM, state-of-the-art SRAM circuits which tackle the issue are
reviewed. Then, devices and circuits to reduce the values of Vmin to the sub-1-V region,
such as ∆Vt-scalable FinFETs and low-Vt0 low-leakage circuits utilizing the gate-source
back-biasing scheme, are discussed. In the second half, the power-supply integrity
issues are described. In addition to new architectures such as multi-core MPUs, and 3-
D thermally conscious chip integration for compact subsystems, drastic reduction in
memory-array area of small cores and chips is particularly vital to ensure integrity, since
the array dominates their area. Thus, a logic-process-compatible FinFET DRAM cell,
achieved using a unique cell and array selection scheme, is proposed. Finally, a scenario
for achieving sub-0.5-V supply in nanoscale CMOS is presented.
ISSCC, SSCS, JSSCC, & IEEE AWARD PRESENTATIONS 9:50AM
BREAK 10:20AM
1.3 The New Era of Scaling in an SoC World 10:35AM
Mark Bohr, Senior Fellow, Intel, Hillsboro, OR
Traditional MOSFET scaling served our industry well for about 30 years, until limits posed by
leakage and total chip power were reached earlier in this decade. To overcome these limits we
have entered a new era of scaling, where innovations in device materials and transistor
structure are just as important as simple scaling of dimensions for achieving continued
improvements in density and performance. Examples of these types of innovations began
with the introduction of copper and low-resistivity interconnects, followed by strained-silicon
transistors, and more recently, high-к dielectrics along with metal-gate transistors.
Circuit layout has also faced severe challenges in meeting high density and low variability as
minimum feature sizes have scaled below the wavelength of light used for patterning.
Lithography-enhancement techniques such as optical- proximity correction, phase-shift
masks and gridded layout have kept us on track for feature-size scaling. Although traditional
MOSFET scaling techniques have not been good for analog circuits due to degraded transistor
gain gm/gds, reduced dynamic range, and worse, transistor mismatch, modern
microprocessors have successfully incorporated a larger number, and a wider range, of highperformance
analog circuits than in the past due to circuit innovations.
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