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SESSION 7
DRAM
Session Chair: Kazuhiko Kajigaya, Elpida Memory, Sagamihara, Japan
Associate Chair: Heinz Hoenigschmid, Qimonda, Neubiberg, Germany
7.1 1.2V 1.6Gb/s 56nm 6F 2 4Gb DDR3 SDRAM with Hybrid-I/O Sense Amplifier and
Segmented Sub-Array Architecture
8:30 AM
Y. Moon, Y-H. Cho, H-B. Lee, B-H. Jeong, S-H. Hyun, B-C. Kim, I-C. Jeong, S-Y. Seo, J-H. Shin,
S-W. Choi, H-S. Song, J-H. Choi, K-H. Kyung, Y-H. Jun, K. Kim
Samsung Electronics, Hwasung, Korea
A 4Gb DDR3 SDRAM at 1.2V and 1.6Gb/s/pin bandwidth is implemented in a 3M 56nm (2Cu1Al)
process with 173.82mm2 die area. For low-voltage low-power and high-frequency operation,
half-frequency read-latency control, hybrid IOSA, and segmented sub-array architecture are
developed. Standby currents are reduced by 63% and operating currents are reduced by 54%
with tRCD of 9.8ns and tAA of 10.4ns.
7.2 8Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology
9:00 AM
U. Kang, H-J. Chung, S. Heo, S-H. Ahn, H. Lee, S-H. Cha, J. Ahn, D. Kwon, J-H. Kim, J-W. Lee,
H-S. Joo, W-S. Kim, H-K. Kim, E-M. Lee, S-R. Kim, K-H. Ma, D-H. Jang, N-S. Kim, M-S. Choi,
S-J. Oh, J-B. Lee, T-K. Jung, J-H. Yoo, C. Kim
Samsung Electronics, Hwasung, Korea
An 8Gb 4-stack 3D DDR3 DRAM with through-silicon-via (TSV) is presented that decreases the
standby power by 50% and active power by 25%, and increases the I/O speed to 1600Mb/s. The
TSV check and repair scheme increases the assembly yield from 15% to 98%. By providing
extra power pads, power noise is reduced to 100mV even if all 4 ranks are refreshed.
7.3 A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with Controllable Repeater and On-the-Fly
Power-Cut Scheme for Low-Power and High-Speed Mobile Application
9:30 AM
B-H. Jeong, J. Lee, Y-J. Lee, T-J. Kang, J-H. Lee, D-H. Hong, J-H. Kim, E-R. Lee, M-C. Kim,
K-H. Lee, S-I. Park, J-H. Son, S-K. Lee, T-W. Kwon, J-H. Ahn, Y-T. Kim
Hynix Semiconductor, Icheon, Korea
A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut
scheme is fabricated in a 66nm process. The DRAM is targeted for low-power and high-speed
mobile applications. The global I/O lines are optimized with a GIO repeater scheme to overcome
the high loading. The data bandwidth is 1066Mb/s/pin with associated maximum power
consumption of 110mW.
Break 10:00 AM
7.4 A 75nm 7Gb/s/pin 1Gb GDDR5 Graphics Memory Device with Bandwidth-Improvement
Techniques
10:15 AM
R. Kho, D. Boursin, M. Brox, P. Gregorius, H. Hoenigschmid, B. Kho, S. Kieser, D. Kehrer,
M. Kuzmenka, U. Moeller, P. Petkov, M. Plan, M. Richter, I. Russell, K. Schiller, R. Schneider,
K. Swaminathan, B. Weber, J. Weber, I. Bormann, F. Funfrock, W. Spirkl, H. Steffens, J. Weller,
T. Hein, M. Gjukic
Qimonda, Neubiberg, Germany
A 1Gb GDDR5 DRAM is fabricated in a conventional 75nm DRAM process. To improve existing
data transfer rates, we implement a boosting transmitter to open the data eye by 100mV, and a
high-speed multiple-domain internal VINT power-generator system to limit on-chip power noise in
critical blocks to 10mV. A data-transfer rate of 7Gb/s/pin is achieved with a 1.5V supply.
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