MicroBlaze Processor Reference Guide (UG081) - Xilinx

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Chapter 2: MicroBlaze Architecture Table 2-1: Configurable Feature Overview by MicroBlaze Version Feature AXI4 (M_AXI_DC) protocol for D- Cache MicroBlaze Versions v7.00 v7.10 v7.20 v7.30 v8.00 v8.10 v8.20 - - - - option option option AXI4 (M_AXI_IC) protocol for I-Cache - - - - option option option AXI4 protocol for stream accesses - - - - option option option Fault tolerant features - - - - option option option Tool selectable endianness - - - - option option option Force distributed RAM for cache tags - - - - option option option Configurable cache data widths - - - - option option option Count Leading Zeros instruction - - - - - option option Memory Barrier instruction - - - - - Yes Yes Stack overflow and underflow detection - - - - - option option Allow stream instructions in user mode - - - - - option option Lockstep support option Configurable use of FPGA primitives option 1. Used in Virtex ® -4 and subsequent families, for saving MUL18 and DSP48 primitives. 12 www.xilinx.com MicroBlaze Processor Reference Guide UG081 (v13.2)
Data Types and Endianness Data Types and Endianness MicroBlaze uses Big-Endian or Little-Endian format to represent data, depending on the parameter C_ENDIANNESS. The hardware supported data types for MicroBlaze are word, half word, and byte. When using the reversed load and store instructions LHUR, LWR, SHR and SWR, the bytes in the data are reversed, as indicated by the byte-reversed order. The bit and byte organization for each type is shown in the following tables. Table 2-2: Word Data Type Big-Endian Byte Address n n+1 n+2 n+3 Big-Endian Byte Significance MSByte LSByte Big-Endian Byte Order n n+1 n+2 n+3 Big-Endian Byte-Reversed Order n+3 n+2 n+1 n Little-Endian Byte Address n+3 n+2 n+1 n Little-Endian Byte Significance MSByte LSByte Little-Endian Byte Order n+3 n+2 n+1 n Little-Endian Byte-Reversed Order n n+1 n+2 n+3 Bit Label 0 31 Bit Significance MSBit LSBit Table 2-3: Half Word Data Type Big-Endian Byte Address n n+1 Big-Endian Byte Significance MSByte LSByte Big-Endian Byte Order n n+1 Big-Endian Byte-Reversed Order n+1 n Little-Endian Byte Address n+1 n Little-Endian Byte Significance MSByte LSByte Little-Endian Byte Order n+1 n Little-Endian Byte-Reversed Order n n+1 Bit Label 0 15 Bit Significance MSBit LSBit Table 2-4: Byte Data Type Byte Address n Bit Label 0 7 Bit Significance MSBit LSBit MicroBlaze Processor Reference Guide www.xilinx.com 13 UG081 (v13.2)
Page 1 and 2: MicroBlaze Processor Reference Guid
Page 3 and 4: Date Version Revision 06/25/07 8.0
Page 5 and 6: Table of Contents Revision History
Page 7 and 8: Introduction Guide Contents Convent
Page 9 and 10: MicroBlaze Architecture Overview IX
Page 11: Table 2-1: Configurable Feature Ove
Page 15 and 16: Table 2-5: Instruction Set Nomencla
Page 17 and 18: Table 2-6: MicroBlaze Instruction S
Page 23 and 24: Instructions a word. For both instr
Page 25 and 26: Special Purpose Registers Program C
Page 27 and 28: Table 2-9: Machine Status Register
Page 29 and 30: Exception Address Register (EAR) Re
Page 31 and 32: Registers Table 2-12: Exception Spe
Page 33 and 34: Floating Point Status Register (FSR
Page 35 and 36: Process Identifier Register (PID) R
Page 37 and 38: Translation Look-Aside Buffer Low R
Page 39 and 40: Translation Look-Aside Buffer High
Page 41 and 42: Translation Look-Aside Buffer Index
Page 43 and 44: Processor Version Register (PVR) Re
Page 45 and 46: Table 2-26: Processor Version Regis
Page 47 and 48: Table 2-29: Processor Version Regis
Page 49 and 50: Pipeline Architecture Pipeline Arch
Page 51 and 52: Memory Architecture Memory Architec
Page 53 and 54: Virtual-Memory Management Real Mode
Page 55 and 56: Virtual-Memory Management System so
Page 57 and 58: TLBLO: TLB Entry Format Virtual-Mem
Page 59 and 60: Virtual-Memory Management system so
Page 61 and 62: Virtual-Memory Management A TLB ent
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Reset, Interrupts, Exceptions, and
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Exception Causes Reset, Interrupts,
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Breaks Equivalent Pseudocode Reset,
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User Vector (Exception) Reset, Inte
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Instruction Cache Operation Instruc
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General Data Cache Functionality Da
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Data Cache memory before reading ba
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Rounding Operations Floating Point
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float sum, t; int i; sum = 0.0f; fo
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Debug and Trace Debug Overview Trac
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Fault Tolerance The LMB BRAM Interf
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eturn XST_FAILURE; } Fault Toleranc
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Small Typical Full Fault Tolerance
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MicroBlaze Partition BRAM MicroBlaz
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Chapter 3 MicroBlaze Signal Interfa
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Table 3-1: Summary of MicroBlaze Co
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AXI4 Interface Description cache is
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Local Memory Bus (LMB) Interface De
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Clk Addr Byte_Enable Data_Write AS
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Slave FSL Signal Interface FSL Tran
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CacheLink Signal Interface The Cach
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Xilinx CacheLink (XCL) Interface De
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Lockstep Interface Description Lock
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Table 3-11: MicroBlaze Lockstep Com
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Table 3-11: MicroBlaze Lockstep Com
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Debug Interface Description Trace I
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Table 3-14: Type of Trace Exception
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Table 3-15: MPD Parameters (Continu
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Chapter 4 MicroBlaze Application Bi
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Stack Convention Stack Convention T
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Calling Convention Memory Model Sma
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Chapter 5 MicroBlaze Instruction Se
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Formats Type A MicroBlaze uses two
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addi Arithmetic Add Immediate Descr
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andi Logial AND with Immediate Desc
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andni Logical AND NOT with Immediat
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eqi Branch Immediate if Equal Descr
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gei Branch Immediate if Greater or
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gti Branch Immediate if Greater Tha
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lei Branch Immediate if Less or Equ
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lti Branch Immediate if Less Than D
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nei Branch Immediate if Not Equal D
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Note Instructions The instructions
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Registers Altered rD PC Latency N
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ki Break Immediate Description Inst
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si Barrel Shift Immediate Descripti
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cmp Integer Compare Description Ins
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frsub Reverse Floating Point Arithm
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fdiv Floating Point Arithmetic Divi
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Table 5-2: Floating Point Compariso
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fint Floating Point Convert Float t
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get get from stream interface tneag
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getd get from stream interface dyna
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idiv Integer Divide Description Ins
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lbu Load Byte Unsigned Description
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lhu Load Halfword Unsigned Descript
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lw Load Word Description Instructio
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lwx Load Word Exclusive lwx rD, rA,
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mbar Memory Barrier Description Ins
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Instructions The value read from FS
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msrset Read MSR and set bits in MSR
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The SLR and SHR are only valid as a
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mulh Multiply High Description Inst
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mulhsu Multiply High Signed Unsigne
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or Logical OR Description Instructi
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pcmpbf Pattern Compare Byte Find De
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pcmpne Pattern Compare Not Equal De
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Registers Altered Latency Note MSR
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Registers Altered Latency Note MSR
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subi Arithmetic Reverse Subtract Im
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tid Return from Interrupt rn from I
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tsd Return from Subroutine Descript
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sbi Store Byte Immediate Descriptio
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sext8 Sign Extend Byte Description
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shi Store Halfword Immediate Descri
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src Shift Right with Carry Descript
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sw Store Word Description Instructi
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swx Store Word Exclusive swx rD, rA
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wdc Write to Data Cache wdc wdc.flu
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wic Write to Instruction Cache Desc
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xori Logical Exclusive OR with Imme
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Additional Resources EDK Documentat
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MicroBlaze Processor Reference Guide (UG081) - Xilinx

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