MicroBlaze Processor Reference Guide (UG081) - Xilinx

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Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Continued) Type A 0-5 6-10 11-15 16-20 21-31 Type B 0-5 6-10 11-15 16-31 TNCAPUT Ra,FSLx 011011 00000 Ra 1N1TA0000000 & FSLx OR Rd,Ra,Rb 100000 Rd Ra Rb 00000000000 Rd := Ra or Rb AND Rd,Ra,Rb 100001 Rd Ra Rb 00000000000 Rd := Ra and Rb XOR Rd,Ra,Rb 100010 Rd Ra Rb 00000000000 Rd := Ra xor Rb ANDN Rd,Ra,Rb 100011 Rd Ra Rb 00000000000 Rd := Ra and Rb FSLx := Ra (control write, blocking if N = 0) MSR[C] := FSLx_M_Full if N = 1 PCMPBF Rd,Ra,Rb 100000 Rd Ra Rb 10000000000 Rd := 1 if (Rb[0:7] = Ra[0:7]) else Rd := 2 if (Rb[8:15] = Ra[8:15]) else Rd := 3 if (Rb[16:23] = Ra[16:23]) else Rd := 4 if (Rb[24:31] = Ra[24:31]) else Rd := 0 PCMPEQ Rd,Ra,Rb 100010 Rd Ra Rb 10000000000 Rd := 1 if (Rd = Ra) else Rd := 0 PCMPNE Rd,Ra,Rb 100011 Rd Ra Rb 10000000000 Rd := 1 if (Rd != Ra) else Rd := 0 SRA Rd,Ra 100100 Rd Ra 0000000000000001 Rd := s(Ra >> 1) C := Ra[31] SRC Rd,Ra 100100 Rd Ra 0000000000100001 Rd := C & (Ra >> 1) C := Ra[31] SRL Rd,Ra 100100 Rd Ra 0000000001000001 Rd := 0 & (Ra >> 1) C := Ra[31] SEXT8 Rd,Ra 100100 Rd Ra 0000000001100000 Rd := s(Ra[24:31]) SEXT16 Rd,Ra 100100 Rd Ra 0000000001100001 Rd := s(Ra[16:31]) CLZ Rd, Ra 100100 Rd Ra 0000000011100000 Rd = clz(Ra) Semantics WIC Ra,Rb 100100 00000 Ra Rb 00001101000 ICache_Line[Ra >> 4].Tag := 0 if (C_ICACHE_LINE_LEN = 4) ICache_Line[Ra >> 5].Tag := 0 if (C_ICACHE_LINE_LEN = 8) WDC Ra,Rb 100100 00000 Ra Rb 00001100100 Cache line is cleared, discarding stored data. DCache_Line[Ra >> 4].Tag := 0 if (C_DCACHE_LINE_LEN = 4) DCache_Line[Ra >> 5].Tag := 0 if (C_DCACHE_LINE_LEN = 8) WDC.FLUSH Ra,Rb 100100 00000 Ra Rb 00001110100 Cache line is flushed, writing stored data to memory, and then cleared. Used when C_DCACHE_USE_WRITEBACK = 1. 18 www.xilinx.com MicroBlaze Processor Reference Guide UG081 (v13.2)
Table 2-6: MicroBlaze Instruction Set Summary (Continued) Type A 0-5 6-10 11-15 16-20 21-31 Type B 0-5 6-10 11-15 16-31 Instructions WDC.CLEAR Ra,Rb 100100 00000 Ra Rb 00001110110 Cache line with matching address is cleared, discarding stored data. Used when C_DCACHE_USE_WRITEBACK = 1. MBAR Imm 101110 Imm 00010 0000000000000100 PC := PC + 4; Wait for memory accesses. MTS Sd,Ra 100101 00000 Ra 11 & Sd SPR[Sd] := Ra, where: SPR[0x0001] is MSR SPR[0x0007] is FSR SPR[0x0800] is SLR SPR[0x0802] is SHR SPR[0x1000] is PID SPR[0x1001] is ZPR SPR[0x1002] is TLBX SPR[0x1003] is TLBLO SPR[0x1004] is TLBHI SPR[0x1005] is TLBSX MFS Rd,Sa 100101 Rd 00000 10 & Sa Rd := SPR[Sa], where: SPR[0x0000] is PC SPR[0x0001] is MSR SPR[0x0003] is EAR SPR[0x0005] is ESR SPR[0x0007] is FSR SPR[0x000B] is BTR SPR[0x000D] is EDR SPR[0x0800] is SLR SPR[0x0802] is SHR SPR[0x1000] is PID SPR[0x1001] is ZPR SPR[0x1002] is TLBX SPR[0x1003] is TLBLO SPR[0x1004] is TLBHI SPR[0x2000 to 0x200B] is PVR[0 to 11] MSRCLR Rd,Imm 100101 Rd 00001 00 & Imm14 Rd := MSR MSR := MSR and Imm14 MSRSET Rd,Imm 100101 Rd 00000 00 & Imm14 Rd := MSR MSR := MSR or Imm14 BR Rb 100110 00000 00000 Rb 00000000000 PC := PC + Rb BRD Rb 100110 00000 10000 Rb 00000000000 PC := PC + Rb BRLD Rd,Rb 100110 Rd 10100 Rb 00000000000 PC := PC + Rb Rd := PC Semantics MicroBlaze Processor Reference Guide www.xilinx.com 19 UG081 (v13.2)
Page 1 and 2: MicroBlaze Processor Reference Guid
Page 3 and 4: Date Version Revision 06/25/07 8.0
Page 5 and 6: Table of Contents Revision History
Page 7 and 8: Introduction Guide Contents Convent
Page 9 and 10: MicroBlaze Architecture Overview IX
Page 11 and 12: Table 2-1: Configurable Feature Ove
Page 13 and 14: Data Types and Endianness Data Type
Page 15 and 16: Table 2-5: Instruction Set Nomencla
Page 17: Table 2-6: MicroBlaze Instruction S
Page 21 and 22: Table 2-6: MicroBlaze Instruction S
Page 23 and 24: Instructions a word. For both instr
Page 25 and 26: Special Purpose Registers Program C
Page 27 and 28: Table 2-9: Machine Status Register
Page 29 and 30: Exception Address Register (EAR) Re
Page 31 and 32: Registers Table 2-12: Exception Spe
Page 33 and 34: Floating Point Status Register (FSR
Page 35 and 36: Process Identifier Register (PID) R
Page 37 and 38: Translation Look-Aside Buffer Low R
Page 39 and 40: Translation Look-Aside Buffer High
Page 41 and 42: Translation Look-Aside Buffer Index
Page 43 and 44: Processor Version Register (PVR) Re
Page 45 and 46: Table 2-26: Processor Version Regis
Page 47 and 48: Table 2-29: Processor Version Regis
Page 49 and 50: Pipeline Architecture Pipeline Arch
Page 51 and 52: Memory Architecture Memory Architec
Page 53 and 54: Virtual-Memory Management Real Mode
Page 55 and 56: Virtual-Memory Management System so
Page 57 and 58: TLBLO: TLB Entry Format Virtual-Mem
Page 59 and 60: Virtual-Memory Management system so
Page 61 and 62: Virtual-Memory Management A TLB ent
Page 63 and 64: Reset, Interrupts, Exceptions, and
Page 65 and 66: Exception Causes Reset, Interrupts,
Page 67 and 68: Breaks Equivalent Pseudocode Reset,
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User Vector (Exception) Reset, Inte
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Instruction Cache Operation Instruc
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General Data Cache Functionality Da
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Data Cache memory before reading ba
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Rounding Operations Floating Point
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float sum, t; int i; sum = 0.0f; fo
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Debug and Trace Debug Overview Trac
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Fault Tolerance The LMB BRAM Interf
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eturn XST_FAILURE; } Fault Toleranc
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Small Typical Full Fault Tolerance
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MicroBlaze Partition BRAM MicroBlaz
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Chapter 3 MicroBlaze Signal Interfa
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Table 3-1: Summary of MicroBlaze Co
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Page 101 and 102:
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AXI4 Interface Description cache is
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Local Memory Bus (LMB) Interface De
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Clk Addr Byte_Enable Data_Write AS
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Slave FSL Signal Interface FSL Tran
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CacheLink Signal Interface The Cach
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Xilinx CacheLink (XCL) Interface De
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Lockstep Interface Description Lock
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Table 3-11: MicroBlaze Lockstep Com
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Table 3-11: MicroBlaze Lockstep Com
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Debug Interface Description Trace I
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Table 3-14: Type of Trace Exception
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Table 3-15: MPD Parameters (Continu
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Chapter 4 MicroBlaze Application Bi
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Stack Convention Stack Convention T
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Calling Convention Memory Model Sma
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Chapter 5 MicroBlaze Instruction Se
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Formats Type A MicroBlaze uses two
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addi Arithmetic Add Immediate Descr
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andi Logial AND with Immediate Desc
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andni Logical AND NOT with Immediat
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eqi Branch Immediate if Equal Descr
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gei Branch Immediate if Greater or
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gti Branch Immediate if Greater Tha
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lei Branch Immediate if Less or Equ
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lti Branch Immediate if Less Than D
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nei Branch Immediate if Not Equal D
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Note Instructions The instructions
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Registers Altered rD PC Latency N
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ki Break Immediate Description Inst
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si Barrel Shift Immediate Descripti
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cmp Integer Compare Description Ins
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frsub Reverse Floating Point Arithm
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fdiv Floating Point Arithmetic Divi
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Table 5-2: Floating Point Compariso
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fint Floating Point Convert Float t
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get get from stream interface tneag
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getd get from stream interface dyna
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idiv Integer Divide Description Ins
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lbu Load Byte Unsigned Description
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lhu Load Halfword Unsigned Descript
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lw Load Word Description Instructio
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lwx Load Word Exclusive lwx rD, rA,
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mbar Memory Barrier Description Ins
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Instructions The value read from FS
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msrset Read MSR and set bits in MSR
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The SLR and SHR are only valid as a
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mulh Multiply High Description Inst
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mulhsu Multiply High Signed Unsigne
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or Logical OR Description Instructi
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pcmpbf Pattern Compare Byte Find De
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pcmpne Pattern Compare Not Equal De
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Registers Altered Latency Note MSR
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Registers Altered Latency Note MSR
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subi Arithmetic Reverse Subtract Im
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tid Return from Interrupt rn from I
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tsd Return from Subroutine Descript
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sbi Store Byte Immediate Descriptio
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sext8 Sign Extend Byte Description
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shi Store Halfword Immediate Descri
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src Shift Right with Carry Descript
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sw Store Word Description Instructi
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swx Store Word Exclusive swx rD, rA
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wdc Write to Data Cache wdc wdc.flu
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wic Write to Instruction Cache Desc
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xori Logical Exclusive OR with Imme
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Additional Resources EDK Documentat
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MicroBlaze Processor Reference Guide (UG081) - Xilinx

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