MicroBlaze Processor Reference Guide (UG081) - Xilinx

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Chapter 2: MicroBlaze Architecture Table 2-21: Translation Look-Aside Buffer High Register (TLBHI) (Continued) Bits Name Description 26 E Endian When this bit is set to 1, a the page is accessed as a little endian page if C_ENDIANNESS is 0, or as a big endian page otherwise. When cleared to 0, the page is accessed as a big endian page if C_ENDIANNESS is 0, or as a little endian page otherwise. The E bit only affects data read or data write accesses. Instruction accesses are not affected.. Read/Write 27 U0 User Defined This bit is fixed to 0, since there are no user defined storage attributes on MicroBlaze. Read Only 28:31 Reserved Reset Value 40 www.xilinx.com MicroBlaze Processor Reference Guide UG081 (v13.2) 0 0
Translation Look-Aside Buffer Index Register (TLBX) Registers The Translation Look-Aside Buffer Index Register is used as an index to the Unified Translation Look-Aside Buffer (UTLB) when accessing the TLBLO and TLBHI registers. It is controlled by the C_USE_MMU configuration option on MicroBlaze. The register is only implemented if C_USE_MMU is greater than 1, and C_AREA_OPTIMIZED is set to 0. When accessed with the MFS and MTS instructions, the TLBX is specified by setting Sa = 0x1002. Figure 2-16 illustrates the TLBX register and Table 2-22 provides bit descriptions and reset values. 0 26 31 MISS Reserved INDEX Figure 2-16: TLBX Table 2-22: Translation Look-Aside Buffer Index Register (TLBX) Bits Name Description Reset Value 0 MISS TLB Miss This bit is cleared to 0 when the TLBSX register is written with a virtual address, and the virtual address is found in a TLB entry. The bit is set to 1 if the virtual address is not found. It is also cleared when the TLBX register itself is written. Read Only Can be read if the memory management special registers parameter C_MMU_TLB_ACCESS > 0. 1:25 Reserved 26:31 INDEX TLB Index This field is used to index the Translation Look-Aside Buffer entry accessed by the TLBLO and TLBHI registers. The field is updated with a TLB index when the TLBSX register is written with a virtual address, and the virtual address is found in the corresponding TLB entry. Read/Write Can be read and written if the memory management special registers parameter C_MMU_TLB_ACCESS > 0. MicroBlaze Processor Reference Guide www.xilinx.com 41 UG081 (v13.2) 0 000000
Page 1 and 2: MicroBlaze Processor Reference Guid
Page 3 and 4: Date Version Revision 06/25/07 8.0
Page 5 and 6: Table of Contents Revision History
Page 7 and 8: Introduction Guide Contents Convent
Page 9 and 10: MicroBlaze Architecture Overview IX
Page 11 and 12: Table 2-1: Configurable Feature Ove
Page 13 and 14: Data Types and Endianness Data Type
Page 15 and 16: Table 2-5: Instruction Set Nomencla
Page 17 and 18: Table 2-6: MicroBlaze Instruction S
Page 23 and 24: Instructions a word. For both instr
Page 25 and 26: Special Purpose Registers Program C
Page 27 and 28: Table 2-9: Machine Status Register
Page 29 and 30: Exception Address Register (EAR) Re
Page 31 and 32: Registers Table 2-12: Exception Spe
Page 33 and 34: Floating Point Status Register (FSR
Page 35 and 36: Process Identifier Register (PID) R
Page 37 and 38: Translation Look-Aside Buffer Low R
Page 39: Translation Look-Aside Buffer High
Page 43 and 44: Processor Version Register (PVR) Re
Page 45 and 46: Table 2-26: Processor Version Regis
Page 47 and 48: Table 2-29: Processor Version Regis
Page 49 and 50: Pipeline Architecture Pipeline Arch
Page 51 and 52: Memory Architecture Memory Architec
Page 53 and 54: Virtual-Memory Management Real Mode
Page 55 and 56: Virtual-Memory Management System so
Page 57 and 58: TLBLO: TLB Entry Format Virtual-Mem
Page 59 and 60: Virtual-Memory Management system so
Page 61 and 62: Virtual-Memory Management A TLB ent
Page 63 and 64: Reset, Interrupts, Exceptions, and
Page 65 and 66: Exception Causes Reset, Interrupts,
Page 67 and 68: Breaks Equivalent Pseudocode Reset,
Page 69 and 70: User Vector (Exception) Reset, Inte
Page 71 and 72: Instruction Cache Operation Instruc
Page 73 and 74: General Data Cache Functionality Da
Page 75 and 76: Data Cache memory before reading ba
Page 77 and 78: Rounding Operations Floating Point
Page 79 and 80: float sum, t; int i; sum = 0.0f; fo
Page 81 and 82: Debug and Trace Debug Overview Trac
Page 83 and 84: Fault Tolerance The LMB BRAM Interf
Page 85 and 86: eturn XST_FAILURE; } Fault Toleranc
Page 87 and 88: Small Typical Full Fault Tolerance
Page 89 and 90: MicroBlaze Partition BRAM MicroBlaz
Page 91 and 92:
Chapter 3 MicroBlaze Signal Interfa
Page 93 and 94:
Table 3-1: Summary of MicroBlaze Co
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101 and 102:
Page 103 and 104:
AXI4 Interface Description cache is
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Local Memory Bus (LMB) Interface De
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Clk Addr Byte_Enable Data_Write AS
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Page 111 and 112:
Page 113 and 114:
Slave FSL Signal Interface FSL Tran
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CacheLink Signal Interface The Cach
Page 117 and 118:
Xilinx CacheLink (XCL) Interface De
Page 119 and 120:
Lockstep Interface Description Lock
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Table 3-11: MicroBlaze Lockstep Com
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Table 3-11: MicroBlaze Lockstep Com
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Debug Interface Description Trace I
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Table 3-14: Type of Trace Exception
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Table 3-15: MPD Parameters (Continu
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Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
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Chapter 4 MicroBlaze Application Bi
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Stack Convention Stack Convention T
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Calling Convention Memory Model Sma
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Chapter 5 MicroBlaze Instruction Se
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Formats Type A MicroBlaze uses two
Page 149 and 150:
addi Arithmetic Add Immediate Descr
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andi Logial AND with Immediate Desc
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andni Logical AND NOT with Immediat
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eqi Branch Immediate if Equal Descr
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gei Branch Immediate if Greater or
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gti Branch Immediate if Greater Tha
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lei Branch Immediate if Less or Equ
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lti Branch Immediate if Less Than D
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nei Branch Immediate if Not Equal D
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Note Instructions The instructions
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Registers Altered rD PC Latency N
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ki Break Immediate Description Inst
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si Barrel Shift Immediate Descripti
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cmp Integer Compare Description Ins
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frsub Reverse Floating Point Arithm
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fdiv Floating Point Arithmetic Divi
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Table 5-2: Floating Point Compariso
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fint Floating Point Convert Float t
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get get from stream interface tneag
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getd get from stream interface dyna
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idiv Integer Divide Description Ins
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lbu Load Byte Unsigned Description
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lhu Load Halfword Unsigned Descript
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lw Load Word Description Instructio
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lwx Load Word Exclusive lwx rD, rA,
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mbar Memory Barrier Description Ins
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Instructions The value read from FS
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msrset Read MSR and set bits in MSR
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The SLR and SHR are only valid as a
Page 207 and 208:
mulh Multiply High Description Inst
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mulhsu Multiply High Signed Unsigne
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or Logical OR Description Instructi
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pcmpbf Pattern Compare Byte Find De
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pcmpne Pattern Compare Not Equal De
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Registers Altered Latency Note MSR
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Registers Altered Latency Note MSR
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subi Arithmetic Reverse Subtract Im
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tid Return from Interrupt rn from I
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tsd Return from Subroutine Descript
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sbi Store Byte Immediate Descriptio
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sext8 Sign Extend Byte Description
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shi Store Halfword Immediate Descri
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src Shift Right with Carry Descript
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sw Store Word Description Instructi
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swx Store Word Exclusive swx rD, rA
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wdc Write to Data Cache wdc wdc.flu
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wic Write to Instruction Cache Desc
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xori Logical Exclusive OR with Imme
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Additional Resources EDK Documentat
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