MicroBlaze Processor Reference Guide (UG081) - Xilinx

Chapter 2: MicroBlaze Architecture
Table 2-9: Machine Status Register (MSR) (Continued)
Bits Name Description Reset Value
29 C Arithmetic Carry
0 = No Carry (Borrow)
1 = Carry (No Borrow)
Read/Write
30 IE Interrupt Enable
0 = Interrupts disabled
1 = Interrupts enabled
Read/Write
31 - Reserved 0
1. The MMU exceptions (Data Storage Exception, Instruction Storage Exception, Data TLB Miss Exception,
Instruction TLB Miss Exception) cannot be disabled, and are not affected by this bit.
2. This bit is only used for integer divide-by-zero or divide overflow signaling. There is a floating point equivalent
in the FSR. The DZO-bit flags divide by zero or divide overflow conditions regardless if the processor is
configured with exception handling or not.
28 www.xilinx.com MicroBlaze Processor Reference Guide
UG081 (v13.2)
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