MicroBlaze Processor Reference Guide (UG081) - Xilinx

Chapter 2: MicroBlaze Architecture
Table 2-25: Processor Version Register 1 (PVR1)
Bits Name Description Value
0:31 USR2 User configured value 2 C_PVR_USER2
Table 2-26: Processor Version Register 2 (PVR2)
Bits Name Description Value
0 DAXI Data side AXI4 in use C_D_AXI
1 DLMB Data side LMB in use C_D_LMB
2 IAXI Instruction side AXI4 in use C_I_AXI
3 ILMB Instruction side LMB in use C_I_LMB
4 IRQEDGE Interrupt is edge triggered C_INTERRUPT_IS_EDGE
5 IRQPOS Interrupt edge is positive C_EDGE_IS_POSITIVE
6 DPLB Data side PLB in use C_D_PLB
7 IPLB Instruction side PLB in use C_I_PLB
8 INTERCON Use PLB interconnect C_INTERCONNECT
9 STREAM Use AXI4-Stream
interconnect
10:11 Reserved
12 FSL Use extended stream (FSL or
AXI) instructions
13 FSLEXC Generate exception for stream
control bit (FSL or AXI)
mismatch
14 MSR Use msrset and msrclr
instructions
15 PCMP Use pattern compare and CLZ
instructions
16 AREA Select implementation to
optimize area with lower
instruction throughput
C_STREAM_INTERCONNECT
C_USE_EXTENDED_FSL_INSTR
C_FSL_EXCEPTION
C_USE_MSR_INSTR
C_USE_PCMP_INSTR
C_AREA_OPTIMIZED
17 BS Use barrel shifter C_USE_BARREL
18 DIV Use divider C_USE_DIV
19 MUL Use hardware multiplier C_USE_HW_MUL > 0
20 FPU Use FPU C_USE_FPU > 0
21 MUL64 Use 64-bit hardware
multiplier
C_USE_HW_MUL = 2
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UG081 (v13.2)