MicroBlaze Processor Reference Guide (UG081) - Xilinx

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Chapter 4: MicroBlaze Application Binary Interface Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Register Usage Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Stack Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Interrupt and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Chapter 5: MicroBlaze Instruction Set Architecture Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Appendix A: Additional Resources EDK Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 MicroBlaze Processor Reference Guide www.xilinx.com 6 UG081 (v13.2)
Introduction Guide Contents Conventions Typographical Chapter 1 The MicroBlaze Processor Reference Guide provides information about the 32-bit soft processor, MicroBlaze, which is part of the Embedded Processor Development Kit (EDK). The document is intended as a guide to the MicroBlaze hardware architecture. This guide contains the following chapters: Chapter 2, “MicroBlaze Architecture,” contains an overview of MicroBlaze features as well as information on Big-Endian and Little-Endian bit-reversed format, 32-bit general purpose registers, cache software support, and Fast Simplex Link interfaces. Chapter 3, “MicroBlaze Signal Interface Description,” describes the types of signal interfaces that can be used to connect MicroBlaze. Chapter 4, “MicroBlaze Application Binary Interface,” describes the Application Binary Interface important for developing software in assembly language for the soft processor. Chapter 5, “MicroBlaze Instruction Set Architecture,” provides notation, formats, and instructions for the Instruction Set Architecture of MicroBlaze. Appendix A, “Additional Resources,” provides links to EDK documentation and additional resources. This document uses the following conventions. An example illustrates each convention. The following typographical conventions are used in this document: Convention Meaning or Use Example Courier font Courier bold Helvetica bold Messages, prompts, and program files that the system displays. Literal commands that you enter in a syntactical statement. Commands that you select from a menu. speed grade: - 100 ngdbuild design_name File Open Keyboard shortcuts Ctrl+C MicroBlaze Processor Reference Guide www.xilinx.com 7 UG081 (v13.2)
Page 1 and 2: MicroBlaze Processor Reference Guid
Page 3 and 4: Date Version Revision 06/25/07 8.0
Page 5: Table of Contents Revision History
Page 9 and 10: MicroBlaze Architecture Overview IX
Page 11 and 12: Table 2-1: Configurable Feature Ove
Page 13 and 14: Data Types and Endianness Data Type
Page 15 and 16: Table 2-5: Instruction Set Nomencla
Page 17 and 18: Table 2-6: MicroBlaze Instruction S
Page 23 and 24: Instructions a word. For both instr
Page 25 and 26: Special Purpose Registers Program C
Page 27 and 28: Table 2-9: Machine Status Register
Page 29 and 30: Exception Address Register (EAR) Re
Page 31 and 32: Registers Table 2-12: Exception Spe
Page 33 and 34: Floating Point Status Register (FSR
Page 35 and 36: Process Identifier Register (PID) R
Page 37 and 38: Translation Look-Aside Buffer Low R
Page 39 and 40: Translation Look-Aside Buffer High
Page 41 and 42: Translation Look-Aside Buffer Index
Page 43 and 44: Processor Version Register (PVR) Re
Page 45 and 46: Table 2-26: Processor Version Regis
Page 47 and 48: Table 2-29: Processor Version Regis
Page 49 and 50: Pipeline Architecture Pipeline Arch
Page 51 and 52: Memory Architecture Memory Architec
Page 53 and 54: Virtual-Memory Management Real Mode
Page 55 and 56: Virtual-Memory Management System so
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TLBLO: TLB Entry Format Virtual-Mem
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Virtual-Memory Management system so
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Virtual-Memory Management A TLB ent
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Reset, Interrupts, Exceptions, and
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Exception Causes Reset, Interrupts,
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Breaks Equivalent Pseudocode Reset,
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User Vector (Exception) Reset, Inte
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Instruction Cache Operation Instruc
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General Data Cache Functionality Da
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Data Cache memory before reading ba
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Rounding Operations Floating Point
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float sum, t; int i; sum = 0.0f; fo
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Debug and Trace Debug Overview Trac
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Fault Tolerance The LMB BRAM Interf
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eturn XST_FAILURE; } Fault Toleranc
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Small Typical Full Fault Tolerance
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MicroBlaze Partition BRAM MicroBlaz
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Chapter 3 MicroBlaze Signal Interfa
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Table 3-1: Summary of MicroBlaze Co
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AXI4 Interface Description cache is
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Local Memory Bus (LMB) Interface De
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Clk Addr Byte_Enable Data_Write AS
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Slave FSL Signal Interface FSL Tran
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CacheLink Signal Interface The Cach
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Xilinx CacheLink (XCL) Interface De
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Lockstep Interface Description Lock
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Table 3-11: MicroBlaze Lockstep Com
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Table 3-11: MicroBlaze Lockstep Com
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Debug Interface Description Trace I
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Table 3-14: Type of Trace Exception
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Table 3-15: MPD Parameters (Continu
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Chapter 4 MicroBlaze Application Bi
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Stack Convention Stack Convention T
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Calling Convention Memory Model Sma
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Chapter 5 MicroBlaze Instruction Se
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Formats Type A MicroBlaze uses two
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addi Arithmetic Add Immediate Descr
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andi Logial AND with Immediate Desc
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andni Logical AND NOT with Immediat
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eqi Branch Immediate if Equal Descr
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gei Branch Immediate if Greater or
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gti Branch Immediate if Greater Tha
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lei Branch Immediate if Less or Equ
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lti Branch Immediate if Less Than D
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nei Branch Immediate if Not Equal D
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Note Instructions The instructions
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Registers Altered rD PC Latency N
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ki Break Immediate Description Inst
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si Barrel Shift Immediate Descripti
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cmp Integer Compare Description Ins
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frsub Reverse Floating Point Arithm
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fdiv Floating Point Arithmetic Divi
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Table 5-2: Floating Point Compariso
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fint Floating Point Convert Float t
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get get from stream interface tneag
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getd get from stream interface dyna
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idiv Integer Divide Description Ins
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lbu Load Byte Unsigned Description
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lhu Load Halfword Unsigned Descript
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lw Load Word Description Instructio
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lwx Load Word Exclusive lwx rD, rA,
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mbar Memory Barrier Description Ins
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Instructions The value read from FS
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msrset Read MSR and set bits in MSR
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The SLR and SHR are only valid as a
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mulh Multiply High Description Inst
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mulhsu Multiply High Signed Unsigne
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or Logical OR Description Instructi
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pcmpbf Pattern Compare Byte Find De
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pcmpne Pattern Compare Not Equal De
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Registers Altered Latency Note MSR
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Registers Altered Latency Note MSR
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subi Arithmetic Reverse Subtract Im
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tid Return from Interrupt rn from I
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tsd Return from Subroutine Descript
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sbi Store Byte Immediate Descriptio
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sext8 Sign Extend Byte Description
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shi Store Halfword Immediate Descri
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src Shift Right with Carry Descript
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sw Store Word Description Instructi
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swx Store Word Exclusive swx rD, rA
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wdc Write to Data Cache wdc wdc.flu
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wic Write to Instruction Cache Desc
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xori Logical Exclusive OR with Imme
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Additional Resources EDK Documentat
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