MicroBlaze Processor Reference Guide (UG081) - Xilinx

Chapter 2: MicroBlaze Architecture
Table 2-20: Translation Look-Aside Buffer Low Register (TLBLO) (Continued)
Bits Name Description Reset Value
23 WR Writable
When bit is set to 1, the page is writable and store
instructions can be used to store data at addresses within
the page.
When bit is cleared to 0, the page is read-only (not
writable). Attempts to store data into a page with a clear
WR bit cause a data storage exception.
Read/Write
24:27 ZSEL Zone Select
This field selects one of 16 zone fields (Z0-Z15) from the
zone-protection register (ZPR).
For example, if ZSEL 0x5, zone field Z5 is selected. The
selected ZPR field is used to modify the access protection
specified by the TLB entry EX and WR fields. It is also
used to prevent access to a page by overriding the TLB V
(valid) field.
Read/Write
28 W Write Through
When the parameter C_DCACHE_USE_WRITEBACK is
set to 1, this bit controls caching policy. A write-through
policy is selected when set to 1, and a write-back policy is
selected otherwise.
This bit is fixed to 1, and write-through is always used,
when C_DCACHE_USE_WRITEBACK is cleared to 0.
Read/Write
29 I Inhibit Caching
When bit is set to 1, accesses to the page are not cached
(caching is inhibited).
When cleared to 0, accesses to the page are cacheable.
Read/Write
30 M Memory Coherent
This bit is fixed to 0, because memory coherence is not
implemented on MicroBlaze.
Read Only
31 G Guarded
When bit is set to 1, speculative page accesses are not
allowed (memory is guarded).
When cleared to 0, speculative page accesses are allowed.
The G attribute can be used to protect memory-mapped
I/O devices from inappropriate instruction accesses.
Read/Write
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UG081 (v13.2)
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