Xilinx Synthesis Technology User Guide

XST User Guide
Table 2-1 VHDL and Verilog Examples and Templates
Macro Blocks Chapter Examples Language Templates
Counters 4-bit Unsigned Up Counter
with Asynchronous Clear
4-bit Unsigned Down
Counter with Synchronous
Set
4-bit Unsigned Up Counter
with Asynchronous Load
from Primary Input
4-bit Unsigned Up Counter
with Synchronous Load with
a Constant
4-bit Unsigned Up Counter
with Asynchronous Clear
and Clock Enable
4-bit Unsigned Up/Down
counter with Asynchronous
Clear
4-bit Signed Up Counter
with Asynchronous Reset
Accumulators 4-bit Unsigned Up Accumulator
with Asynchronous
Clear
4-bit asynchronous counter with
count enable, asynchronous reset
and synchronous load
None
2-8 Xilinx Development System