EECE 353: Digital Systems Design Lecture 10: Datapath ... - Courses

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Now combine the state machine and the datapath into one circuit: Lecture 10, Page 12
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity top is port(A, X : in std_logic_vector(7 downto 0); s, clk : in std_logic; P : out std_logic_vector(7 downto 0); done : out std_logic); end top ; architecture behavioural of top is signal curr_state: std_logic_vector(1 downto 0) := "00"; signal z, sel, selA : std_logic; signal P_int: std_logic_vector(7 downto 0); signal cnt: std_logic_vector(7 downto 0); …. Lecture 10, Page 13
Page 1 and 2: EECE 353: Digital Systems Design Le
Page 3 and 4: Real Systems All but the simplest s
Page 5 and 6: Exponent: A bit more complicated Wh
Page 7 and 8: Consider this simple datapath: If w
Page 9 and 10: We have to let this run for A cycle
Page 11: Here is a simple controller that do
Page 15 and 16: process(clk) begin if (clk’event
Page 17 and 18: Lecture 10, Page 17
Page 19 and 20: Top level diagram of what we will b
Page 21 and 22: State Machine: Lecture 10, Page 21
Page 23 and 24: Serial Multiplier Suppose we want t
Page 25 and 26: Top level diagram of what we will b
Page 27 and 28: State Machine: Lecture 10, Page 27
Page 29 and 30: This datapath looks something like
Page 31 and 32: Fully-Parallel Sorting First consid
Page 33 and 34: Suppose we want to sort k numbers:
Page 35 and 36: Lecture 10, Page 35
Page 37 and 38: Assume that the values to be sorted
Page 39 and 40: State S2: Load Register A with Ri a
Page 41 and 42: State S4: Load value of Rj into B 1
Page 43 and 44: State S5: A and B are compared, and
Page 45 and 46: State 6: Swap Ri and Rj (part 1) 0
Page 47 and 48: State S7: Swap Ri and Rj (part 2) 1
Page 49 and 50: State S8: Load A from Ri 1 0 Lectur
Page 51 and 52: State S8: S9 S1 S2 S8 S3 S7 S4 S5 L
Page 53 and 54: An alternative datapath: Tri-state
Page 55: Summary of this very long lecture W

EECE 353: Digital Systems Design Lecture 10: Datapath ... - Courses

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