Report I: CMOS Baseline Process (pdf) - Berkeley Microlab ...

CMOS BASELINE PROCESS
IN THE
UC BERKELEY MICROFABRICATION LABORATORY
by
Shenqing Fang
Memorandum No. UCB/ERL M95/98
20 December 1995
ELECTRONICS RESEARCH LABORATORY
College of Engineering
University of California, Berkeley, CA 94720

CMOS Baseline Process
in the
UC Berkeley Microfabrication Laboratory
Shenqing Fang
Electronics Research Laboratory
College of Engineering
University of California, Berkeley
December, 1995
Abstract
This project describes the characterization of the Berkeley CMOS Baseline, a joint project by sev-
eral research groups. The process supports 2 (im n-well technology, with double poly-Si, double
metal, and defines the standard process modules in the Microlab. Statistical process control data,'
geometric design rules and BSIM3 SPICE model parameters are presented.

CMOS Baseline Process in the UC Berkeley Microfabrication Laboratory
Table of Contents
1 Introduction . 3
2 Process Design 5
2.1 Process Flow and Device Cross Sections
2.2 Mask Definitions
3 Process Simulation and Material Characterization...., 9
3.1 N-Channel
3.2 P-Channel
3.3 N+Source-Drain
3.4 P+Source-Drain
4 Electrical Measurement Results 15
4.1 HP4145 Measurement Results
4.2 Statistical Measurement Data
5 SPICE Parameter Extraction 28
6 Summary 35
References 36
Appendix A 2 [im N-Well, Double Poly-Si and Double Metal CMOS Process
and Device Parameter Targets 37
Appendix B 2 [im N-Well, Double Poly and Double Metal CMOS Design Rules 38
Appendix C Microlab CMOS Baseline Process Log '. 40

1 Introduction
In an educational laboratory like the UC Berkeley Microfabrication Laboratory, each project is
different and students need to identify a starting point from which they can carry on their own
research. This is one of the reasons why the Microlab reestablished the baseline CMOS process in
April 1992, based on the previous Microlab CMOS process [1]. The baseline also serves to moni-
tor CMOS process equipment, to quickly discover and fix process problems, and to specify stan-
dard process modules for VLSI operations. We have developed both p-well and n-well, 2 (im,
double poly and double metal CMOS processes and while these are.running we embarked upon
developing a 1.3 |im, twin-well, double poly, double metal CMOS process.
Our baseline provides "standard" CMOS circuits to various research groups. The advantage is that
the designers are close to processing, can follow it in detail, can feedback their circuit perfor-
mance results to process engineering and thus improve the process. The baseline has fabricated
lots for several research groups: The Berkeley Sensor and Actuator Center (BSAC), the Berkeley
Computer Aided Manufacturing (BCAM) group, the Solid-State Devices and Technology group,
the Cryoelectronics Research group, and the Integrated Circuits group. The baseline process con-
sists of standard steps. Each process step can also be used as a process module by different groups
for their own process design.
Statistical process control (SPC) has been applied to the baseline. Standard in-line measurements
have been established to monitor critical steps. The electrical test structures, designed by David
Rodriguez [2] for testing on an automatic probe station, enable collection of statistical data. The
test structures are placed in the scribe lanes of each wafer. Tests are performed on each wafer and

the resulting data are statistically analyzed to determine whether the process Is in control.
During the development of our baseline process, we compared the n-well and p-well processes
and found that the n-well process has the advantage of fewer process steps, easier threshold volt-
age control, and better device performance. In this memo we will describe the n-well CMOS
baseline process in detail, with process simulations, materials characterization and electrical mea-
surement results. Process and device parameter targets and circuit design rules are also included.

2 Process Design
The Microlab's 2 Jim, double poly and double metal CMOS process was designed mainly for ana-
log circuit fabrication. The objective is to fabricate good performance 2 (J.m CMOS circuits with a
simple and stable process. The process has 5 implant steps and 11 lithography steps. The starting
material is a 4" 8-12 Q-cm p-type, wafer, on which 2jim N-channel MOSFETs can be fab-
ricated without a punchthrough implant. There is no n-field implant, because the phosphorus con-
centration at the n-well surface is high enough for a field threshold voltage greater than 12V. The
baseline process specifications are given in Appendix A.
2.1 Process Flow and Cross Sections
A brief process flow with device cross sections is shown in Figure 1. All the process steps are
done in the Microlab with the exception of ion implant steps, which are carried out at Ion Implant
Services (Sunnyvale, California). The detailed information is in the process outline in Appendix
C, which includes the equipment used in the Microlab for the CMOS process.
Well Implant
P-Field Implant
Process Step
Threshold Adjustment Implant
N+ S/D Implant
P+ S/D Implant
Ion Implantations
Species
Phosphorus
Boron
Boron
Arsenic
Boron
Energy (KeV)
150
70
30
160
30
Dose (/cm2)
5xl012
l.SxlO13
l.TxlO12
5xl015
5xl015

2.2 Mask Definitions
Mask Name
NWELL
ACTIVE
PFIELD
POLY
CAP-CE
N+S/D
P+S/D
CONT
METAL1
VIA
METAL2
chrome
emulsion
emulsion
emulsion
emulsion
chrome
emulsion
chrome
emulsion
chrome
emulsion
Type
dark
clear
clear
clear
clear
dark
clear
dark .
clear
dark
clear
Field
Align Sequence
NWELL
ACTIVE
ACTIVE
POLY
POLY
POLY
POLY
CONT
METAL1
VIA

2 um CMOS Process Flow and Cross Sections
Phosphorus
1 1 1 1 1 1 I U U H U H
Photoresist
Oxide
p-typeSi 8-12 ohm-cm
Boron
m i u H u u u m u
Photoresist 2
Pad
oxid"ev^
Photoresist 1
' "•%i«*'^v * j
-, ."3®&£'.k* ;„
**•
p-typc Si
Boron
Photoresist 1
^R^^^i-iC;.'!
N-wcll
U t I U \ H H I t i H
v. ' ^~
FOX :
p-type Si
\
N-well
Fig. 1 Process flow and cross sections.
1. Initial oxidation: lOOnm oxide
2. Well photo
3. Well implant:
12 2
phosphorus, 150KeV, 5x10 /cm
4. Well drive-in: Xj = 3.4um
5. Pad oxidation: 30 nm
6. Nitride deposition: lOOnm
7. Active area photo (PR1)
8. Nitride etch
9. P-field photo (PR2)
double photoresist process
10. P-field implant:
13 2
boron, 70KeV, 1.5x10 /cm
11. LOCOS:
field oxide (FOX): 650-700nm
12. Nitride removal
13. Pad oxide removal
14. Sacrificial oxide: 20nm
15. Threshold implant:
boron, 30KeV, 1.7x10 /cm2

p-typc Si
p-type Si
p-type Si
gate poly
Fig. 1 (cont.) Process flow and cross sections.
16. Sacrificial oxide removal
17. Gate oxidation: 30nm
18. Gate poly deposition:
450nm
19. Gate poly photo
20. Gate poly etch
21. Capacitor oxidation:
80nm on poly
22. Capacitor poly deposition:
450nm
23. Capacitor photo
24. Capacitor etch
25. N+ S/D photo
26. N+ S/D implant
As, KSOKeV, SxldVcm2
27. N+ S/D anneal
28. P+ S/D implant
B,30KeV,5xltfs/on?
29. PSG deposition: 700nm
and densiflcation
30. Contact photo
31. Con tact etch
32. Al sputtering: 600nm
33. Al definition
34. PECVD thin oxide: 40nm
35. Spin-On-Glass SOOnm
36. PECVD thick oxide: 300nm
37. VIA photo
38. VIA etch
39. Al sputtering: 800-900nm
40. Al photo
41. Al Etch
42. Sintering

3 Process Simulation and Material Characterization
The results of SUPREM3 and Spreading Resistance Analysis (SRA) are presented here. The SRA
was performed by Solecon Laboratories (San Jose, CA). The SRA samples were made from the
lot cmos39.
3.1 N-Channel
Doping profiles in the N-channel region are shown in Figures 2 and 3. The simulated gate oxide
thickness is 29.2 nm. The simulated surface concentration (3.9xl016/cm2) is about two times of
that from SRA (2xl016/cm2). In Section 4, we will see the SRA result is close to the statistical
data obtained from electrical measurements on cmos39. See Figure 24 (a).
3.2 P-Channel
Figures 4 and 5 are the doping profiles in the P-channel region. From simulation, the well junction
depth and threshold implant junction depth are 3.4231 and 0.24135 |j.m, respectively. SRA data
show a shallower N-well junction of 2.748 (im and no threshold implant junction. However, SRA
P+ source-drain profile in Figure 9 shows an N-well junction depth of 3.224 Jim which is close to
the simulation result.

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Dopant Profile in P-Channel
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i nr ij,
Carrier
Concentration
(cm-3) 101
?PP
0 1 2 3 4 5 (
DEPTH - microns
Date 6/1/95 Probe road 2.8 g Orientation Si
File | SJEC1131 Bevel Angle .02059 Step Increm 5 urn
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22«1 rfMOOl MiVE IAK JOSE, CA 95131 (W«) «35 7V55
0.00 1.00 2.00 3.00
Distance (Microns)
Fig. 5 P-channel dopant profile obtained from SRA.
Fig. 4 P-channel dopant profile simulated by SUPREM3.

3.3 N+ Source-Drain
The simulated As doping profile (Fig. 6) shows a tail which results in a junction depth of 0.7 jim.
An extrapolation of the doping profile without the tail gives a junction depth of 0.31 fim which
agrees with the SRA result (Fig. 7). The sheet resistance calculated from SRA and measured with
the four-point probe on the same sample are 38 and 37 D/square, respectively. From electrical
measurement, the average sheet resistance is 43.64 Q/square (Fig. 29 (a)).
Parameter
Junction Depth, Xj (u\m)
Sheet resistance (Q/square)
3.4 P+ Source-Drain
Simulated
0.31
Measured from
SRA sample
0.313
38
Calculated
from SRA
37
Electrical
Measurement
43.64
The simulated junction depth (Fig.8) is 0.55784 jim, while the SRA junction depth (Fig 9) is
0.645 |im. The sheet resistance calculated from SRA is 67 Q/square. The four-point probe mea-
surement on the same sample shows 51 Q/square. Both are within the range from 51.5 to 67.5 £>
square as can be seen from the average of electrical measurements (Fig. 30 (a)).
Parameter
Junction Depth, Xj (u,m)
Sheet resistance (Q/square)
Simulated
0.55784
Measured from
SRA sample
0.645
51
12
Calculated
from SRA
67
Electrical
Measurement
59.5

log(Concentration (t/cm**3))
cn
a
o
•8 EU
Drr
1-1
O l-h
H-

P+ S/D Dopant Profile
217
19-
g18- Currier
Concentration
(OT-3) 10!*l
Well Implant: Phos., 150 keV, 5E12/cm2
Vt Implant: Boron, 30 keV, l.TE12/cm2
P+ S/D Implant: Boron, 30 keV, 5E15/cm2
Pt S/D Junction Depth: O.SSTB'I microns
PSG Denslfication: 950C, 30 mln.
n-
Net
Boron
— — — — Phosphorus
\
16-
15-
2 3 4
DEPIM - sicrcn*
tot* 6/V93 Prcfa* l£*d 2.8 g ctUntaUon si
riln I SJDG1029 B«V»1 Arigla .021H9 Step Inc«n 2.5 in
U*C,BEKKELEY
o.oo 1.00 2.00 3.00 4.00 5.00
Distance (Microns)
LA'eO'RATO'RIES
1HCO*f«WIt6
2241 PAIUCOH MIVC tM XttC, CA t!13t (UK) Wt 7V$5
Fig. 8 P+ source-drainl dopant profile simulated by SUPREM3, Fig. 9 P+ source-drain dopant profile obtained from SRA.

4 Electrical Measurement Results
The HP4145 Semiconductor Parameter Analyzer and an automatic probe station (autoprober)
were utilized to make electrical measurements on each lot. The autoprober consists of the Electro-
glas Model 200IX, an HP 4085A Switching Matrix, an HP4084 Switching Matrix Controller, an
HP4141A Source/Monitor and a UNIX workstation. The test structures for the autoprober were
designed by D. Rodriguez [2] and they were included in the scribe line of each wafer.
4.1 HP4145 Measurement Results
Figures 10 through 15 are NMOS and PMOS characteristics measured with HP4145. Both
devices have W/L of 10/2.
15

.0000
.0000
ID CuA)
VD .8000/div ( V)
8.000
v«rl«bl«l:
VD -chl
St«rt
Stoo
St«D
st*rt
Scop
St«p
Fig. 10 NMOS drain current vs. drain voltage characteristics.
18.42
1.842
/div
-.0000
.0000
LINE1
LINE2
lecade
/div
1E-12
CURSOR ( 1.2000V 6.883UA . )
MARKER ( 1.2000V . 6.8B3uA . 1
GRAD
15.7E-06
s/r
u_
i /
! 7
V
/
/ft /
x
A /
/
/
,
/f\
/
/ /
//
* // /y
VG .2000/div ( V)
1/SRAD
63.BE+03
Xintercept
7S1E-03
//
/
/
/
//
—
i
2.000
Yintercept!
-11.9E-O6 1
I
Start '
Stoo
Step
-cna
-ens
.oooov
a.oooov
.^ooov
.oooov
7.OOOOV
1. OOOOV
.oooov
.oooov
.OOOOV
2.OOOOV
.O50OV
VSDQ -Ch3
St^rt .OOOOV
Stpp -3.0000V
Step -1. OOOOV
Con*t«nt«:
VO -Chi
VS -CflZ
Fig. 11 NMOS drain current vs. gate voltage characteristics.
CD
t A) CURSOR (
MARKER (
.5500V . 7.90BnA .
.5500V . 7.9O8nA ,
1E-04
1 /
/ ,
^
.
LINE1
LINE2
GRAD
10.4E+00
i
/
y
•f!
\t
1
//
k
VG .2000/dlv (
l/GRAO
96.0E-03
Xintercept
1.33E+00
\0 0
1
— *-
1.400
V] Yintercept
14.7E-15
Fig. 12 NMOS subthreshold characteristics.
16
Start
Stop
Step
St«rt
Stoo
Step
con«t«nt«:
vs -ChZ
VEUB -Cfl3
_O30OV
.OOOOV
-2,OOOOV
a.oooov
.osoov
.oooov
.oooov

.0000
.0000 -10.OO
VO 1.000/div T V)
Fig. 13 PMOS drain current vs. drain voltage characteristics.
ID
CuA) CURSOR C-i. 15OOV . -2,765uA „ 1
MARKER (-1. 1500V .-2.765UA .
y/
]_
\
-6 . 829
/, <
/A
y
.6829
/div
V
/ , / A y ^.
j/ /
1
j \/ y / / A/ i
i
i -7& / /
i i y \/ v /
v/ I
^ i !
\ \e .OOOOV
-.0003
.00 00 -2-000
VG .HOOO/div t V)
GRAD 1 i/GHAO j Xintercept| Yintercept)
LINE11 5.S9E-06! 17BE+03 j -664E-03 ', 3.77E-O6J
LINE2J i 1 i i
Fig. 14 PMOS drain current vs. gate voltage characteristics.
D
t A) CURSOR C- .2500V .-93.90pA .
MARKER (- -2500V -93.90pA .
•iE-0^
7 1
ecade
/div
-1E-12
1
!
i //
GRAD
LINElJ -iO.iE-KK
LINE2
/y
/!/
/y y/
//
i //>
//
(
^
k 4--H
"3r~ T
^G .2000 /div ( V)
i/GHAD
-9B.5E-03
1
vn -oil
i_in«*r cx««g
Scant .OOOO V
Stop -iO.OOOV
St«p - ,2000V
vc -chx
Stare .OOOOV
Stoo -7. OOOOV
St«p -1. OOOOV
Can* tan c«;
vs -cna .oooov
VSUS -Ch3 .COOO V
Stop -Z. OOOOV
Step - .O5OOV
v^U8 -Ch3
Star-t .OOOOV
Stop 3.0000V
St«p 1. OOOOV
VO -Chi - .OSOOV
VC -ChZ . OOOOV
j
\0 0 -i.
400
Xintercept Yintercept!
-1.24E+00 -273E-15 |
Fig. 15 PMOS subthreshold characteristics.
17
V«r labial:
VE -C*lX
t_in«*r «pf*
Start .5000V
Stop
— i.SOOOV
Step - .OSOOV
VO -Chi
Start - .03OOV
Ktoo -B.O300V
St«p -3. OOOOV
Cone tan t«:
vs -cha .oooov
VSUS -Ch3 .OOOOV

4.2 Statistical Measurement Data
Autoprober testing enables the baseline to collect large amounts of data for monitoring the pro-
cess and extracting device parameters. Figures 16 through 31 are the statistical results from auto-
prober measurements. For threshold.voltage, fifty-two dies across each wafer were tested and for
other parameters, ten to twenty dies across each wafer were measured. These measured dies were
uniformly distributed across the wafer. Two sets of data, (a) and (b), are presented here. In (a),
each data point is the average of the measurements on one wafer and is connected by a line indi-
cating a process lot. Avg is the average of the data points in the figures, which is the average of a
wafer. UCL and LCL stand for Upper and Lower Control Limits, respectively. In (b), each point is
the standard deviation across the wafer corresponding to the point in (a).
In effective channel length and width measurements (Fig. 18-21), the resistance and conductance
methods [3,4] were used. Ld and Wd are the parameters in the following equations:
Leff = L - AL = L - 2Ld,
Weff=W-AW = W-2Wd.
In Figures 22 and 23, k'_n and k'_p are the current factors (iCox /2 and were measured while the
devices were at saturation.
18

Since the dopant concentration is not uniform in the ion-implanted channel regions, YI and y2
were extracted at low and high substrate bias [5,6]. Based on these results, dopant concentrations
at the surface and substrate (or n-well for PMOS) were obtained. The surface dopant concentra-
tions are shown in Figures 24 and 25. The surface doping concentrations measured this way can
be used to monitor the process, although they are not precise surface doping concentration mea-
surements.
In Figures 27 and 30, cmos39 was not included, because BF2 was implanted to make shallow P+
S/p.junctions for investigation of 1.3 |im PMOS.
Both NMOS and PMOS source-drain leakage currents were also measured at V^=5V and
Vgs=OV on the wafer cmos40-l. Fifty-two dies, were tested across the wafer. The leakage current
average and standard deviation for NMOS and PMOS are 0.855pA/|im and 0.0487pA/|im, and
-1.99pA/(im and 0.9546pA/|im, respectively.
A summary of the measurements, Process and Device Parameter Targets, is attached in Appendix
A. These parameters will be updated with the improvements in the baseline process. Some capac-
itance parameters will be added after the autoprober capacitance measurement routines are avail-
able to extract capacitance parameters.
19

0.800-
0.775-
0.750-
0.725-
S7
0.700-
0.675-
A
\« cmos39
cmosAO ft j\ cmos38
UCL=0.7885
Avg=0.7440
LCL=0.6996
0.06-1
0.05-
0.00
(b)
onos39
Avg=0.016
Fig. 16 (a) NMOS threshold voltage distribution in the 2um N—well CMOS process. Each data point
is the average of fifty-two dies measured across one wafer. UCL: Upper Control Limit. LCL: Lower
Control Limit, (b) Each data point is the standard deviation corresponding to the data point in (a).
0.85-1 0.10-1
0.65
(a)
UCL=0.816
Avg=0.745
LCL=O.S73
0.00
(b)
cmos39
Avg=0.029
Fig. 17 (a) PMOS threshold voltage distribution in the 2um N-well CMOS process. Each data point
is the average of fifty-two dies measured across one wafer. UCL: Upper Control Limit. LCL: Lower
Control Limit, (b) Each data point is the standard deviation corresponding to the data point in (a).
20

0.5-
0.4-
E 0,3-
(a)
UCL=0.46
Avg=0.24
LCL=0.03
0.25-1
0.00
(b)
cmos39
Avg=0.059
Fig. 18 (a) NMOS effective channel length distribution in the 2um N—well CMOS process. Each data
point is the average of fifty-two dies measured across one wafer. UCL: Upper Control Limit. LCL:
Lower Control Limit, (b) Each data point is the standard deviation corresponding to the data point in (a).
0.5-1
o 4-
0.3-
-1 0.2-
0.1 ~
o.o-
cmos37
,cmos38
cmosAO
(a)
• UCL=0.49
-Avg=0.28
• LCL=0.06
0.15-
0.00
(b)
cmos39
Avg=0.053
Fig. 19 (a) PMOS effective channel length distribution in the 2um N-well CMOS process. Each data
point is the average of fifty-two dies measured across one wafer. UCL: Upper Control Limit. LCL:
Lower Control Limit, (b) Each data point is the standard deviation corresponding to the data point in (a).
21

0.95- cmos37
0.90- A
0.85-
0.80-
0.75-
0.70-
0,65
Q.60-
/ \ cmos39
caos38 \AA A
rA40 1
V--
UCL=0.905
Avg=0.778
LCL=0.652
(a) (b)
Avg=0.054
Fig. 20 (a) NMQS. effective channel width distribution in the 2um N-well CMOS process. Each data
point is the average of fifty-two dies measured across one wafer. UCL: Upper Control Limit. LCL:
Lower Control Limit, (b) Each data point is the standard deviation corresponding to the data point in (a).
Wdp (urn)
1.00-1
onos37
0.95-
0.90-
0.85-
0.80-
0.75-
0.70-
0.65-
0.60-
J
/c»os38 cmos39
cmosAO
4f
ri
0)
UCL=0.989
Avg=0.813
LCU0.638
q
en"
(b)
Avg=0.051
Fig. 21 (a) PMOS effective- channel width distribution in the 2um N-well CMOS process. Each data
point is the average of fifty-two dies measured across one wafer. UCL: Upper Control Limit. LCL:
Lower Control Limit, (b) Each data point is the standard deviation corresponding to the data point in (a).
22

30-
29-
28"
OBOS37
27-
26-
25-
24-
23-
22-
21-
^" cmos40 . .
-A V-
— • « v. *
ris38
^~* c»os39
(a)
UCL=27.8
Avg=24.1
LCL=20.4
Fig. 22 (a) NMOS k' distribution in the 2um N-well CMOS process. Each data point is the average of
ten dies measured across one wafer. UCL: Upper Control Limit. LCL: Lower Control Limit,
(b) Each data point is the standard deviation corresponding to the data point in (a).
17-1
16-
15-
14-
13-
12-
1 1-
1 0'
cmos37
c»os38
cmos40
(a)
cmos39
-UCL=16.2
-Avg=13.4
- LCL=10.5
0.8-
5-
4-
0.7oaos37
0.6-
0.5-
0.4-
0.3-
0.2-
0.1-
1
1
cmos38
(b)
\0
r r v c«os39
(b)
Avg=0.32
Fig. 23 (a) PMO.S k' distribution in the 2um N-well CMOS process. Each data point is the average of
ten dies measured across one wafer. UCL: Upper Control Limit. LCL: Lower Control Limit,
(b) Each data point is the standard deviation corresponding to the data point in (a).
23

I
UCL=1.78
LCL=0.62
0.20-
°-10-
0.05_
o.oo-
c»os37
onos38
(a) (b)
ca»os39
-Avg=0.085
Fig. 24 (a) NMOS surface dopant concentration (Ns) distribution in the 2um N-well CMOS process.
Ns was extracted from gammal measurement. Each data point is the average of ten dies measured
across one wafer. UCL: Upper Control Limit. LCL: Lower Control Limit, (b) Each data point is the
standard deviation corresponding to the data point in (a).
°i
\
cmos37
000538
cmosAO
(a)
c=,os39
- UCL=8.7
• Avg=4.6 £.
q
CO
- LCU0.4
2.0-1
cmos37
1.0-
0.5-
0.0-
cmos38
«
\O
(b)
cmos39
-Avg=0.39
Fig. 25 (a) PMOS surface dopant concentration (Ns) distribution in the 2um N-well CMOS process.
Ns was extracted from gammal measurement. Each data point is the average often dies measured
across one wafer. UCL: Upper Control Limit. LCL: Lower Control Limit, (b) Each data point is the
standard deviation corresponding to the data point in (a).
24

40-
35-
30-
25-
20-
cmos38
1
1 5
— Jt !iAr-»^— X-« = Ava-15 1
-* V cmbs39
1 0-
cmos37 »^v«-»»^»«
6-
5-
4-
Q
t i/-«r i-,^ ^v CO _
C

cmos38
^^* *,
cnxos^O
(a)
cmos39
- UCL=3.20
-Avg=2.24
-LCU1.27
0.0
(b)
Avg=0.25
Fig. 28 (a) Al—Poly contact resistance distribution in the 2um N—well CMOS process. Each data point
is the average of fifty-two dies measured across one wafer. UCL: Upper Control Limit. LCL: Lower
Control Limit, (b) Each data point is the standard deviation corresponding to the data point in (a).
52.5-1
50.0-
UCL=49.31
LCL=37.94
8-1
6-
cmos39
Avg=1.6
Fig. 29 (a) N+ diffusion sheet resistance distribution in the 2um N-well CMOS process. Each data point
is the average of fifty-two dies measured across one wafer. UCL: Upper Control Limit. LCL: Lower
Control Limit, (b) Each data point is the standard deviation corresponding to the data point in (a).
26

70-1
65-
60-
55-
50-
cmos37
cmos38
cmosAO
- UCL=67.5
-Avg=59.5 ~f
-UCL=51.5
(a) (b)
Avg=2.4
Pig. 30 (a) P-t- diffusion sheet resistance distribution in the 2um N-well CMOS process. Each data point
is the average of fifty-two dies measured across one wafer. UCL: Upper Control Limit. LCL: Lower
Control Limit, (b) Each data point is the standard deviation corresponding to the data point in (a).
17-
UCL=16.6
LCL=13.7
o~
1Q
Q
to
o CL
«
a:
1.6-
1.4-
1.2-
1.0-
0.8-
0.6-
0.4-
n •> —
cmos38
I
ft
\0
f /\
\ v *^*
u AAA/^
onos37 cmos39
(b)
Avg=0.73
Fig. 31 (a) Doped poly sheet resistance distribution in the 2um N-well CMOS process. Each data point
is the average of fifty-two dies measured across one wafer. UCL: Upper Control Limit. LCL: Lower
Control Limit, (b) Each data point is the standard deviation corresponding to the data point in (a).
27

5 SPICE Parameter Extraction
Parameters for BSIM3, a SPICE model developed by the device group at UC Berkeley [7], was
extracted by BSIMPro [8]. Figures 32 and 33 contain I-V characteristics of both NMOS and
PMOS. Some extraction results are shown in Figures 34 through 36. On the next two pages are the
output of BSIMPro. This data does not include capacitance parameters. These will be added
when the capacitance measurement routines are available for the autoprober.
28

Output of BSIMPro:
*model = bsim3
*Cadence Compatibility Mode
*LogName=cmos40 UserName=sfang Date=07-13-1995
* Lmin= 2 Lmax= 25 Wmin= 5 Wmax= 50
*
* GENERAL PARAMETERS
*
.model NMOS NMOS
+Level= 10
+Tnom=27.0
+Npeak= 6.906394E+16 Tox=3.27000E-08 Xj=3.00000E-07
+dl= 1.96500E-07 dw= 6.98499977588654E-07
+SatMod=2 SubthMod=2
+BulkMod= 1
*
* THRESHOLD VOLTAGE PARAMETERS
*
+VthO= .7476673 Phi= .7949965 Kl= 1.433851 K2=-,2482773 K3= 46.17294
+DvtO= . 5664904 Dvtl=. 53 11641 Dvt2=-.7567183
+Nlx=0 WO- 2.088732E-05
+K3b=- 17.6259
*
* MOBILITY PARAMETERS
+Vsat= 107632.1 Ua=2.175036E-09 Ub=-2.723978E-18 Uc=-7.168329E-03
+RdsO=71.9 Rdsw=769 U0= 670
+A0=. 3 190749
+Keta— 2.304753E-02 Al= 5.444023E-02 A2= .7
*
* SUBTHRESHOLD CURRENT PARAMETERS
+Voff=-,0551213 NFactor^. 98 18507 Cit=-1.738184E-04
+Cdsc=-1.186696E-04'Vglow=-.12 Vghigh=.12 '
+Cd-scb=-2.228673E-05
+EtaO= 6.305706E-03 Etab=-1.986577E-02
+Dsub=. 1730233
*
* ROUT PARAMETERS
*
+Pclm= .8851407 Pdibll=. 0171912 Pdibl2=2.364713E-03
+Drout=. 103091 Pscbel=2.085241E+08 Pscbe2= 2.2703 65E-05
+Pvag=-.8659828
+Eta=0 Litl=1.715517E-07
+Ldd- 0
29

* GENERAL PARAMETERS
*
.model PMOS PMOS
+Level= 10
4-Tnom=27.0
+Npeak= 8.734341E+15 Tox=3.27000E-08 Xj=6.50000E-07
+dl= 3.44191E-07 dw= 8.19282412528992E-07
+SatMod=2 SubthMod=2
+BulkMod= 1
*
* THRESHOLD VOLTAGE PARAMETERS
*
+VthO=-.6993924 Phi= .6880878 Kl-.5099099 K2=2.812088E-02 K3=-.l 192135
+DvtO= .9119751 Dvtl=.5007811 Dvt2=-7.716554E-02
+Nlx= 5.441865E-07 WO=-3.535396E-06
+K3b=9.917567E-03
*
* MOBILITY PARAMETERS
*
+Vsat= 213574.9 Ua= 3.401969E-08 Ub=-8..815556E-17 Uc=-.292751
+RdsO= 180.8564 Rdsw= 342,9426 U0= 670
+A0= .655002
+Keta=-2.507999E-02 A1= .0637029 A2= 1.387779E-16
*
* SUBTHRESHOLD CURRENT PARAMETERS
*
+Voff=-5.633137E-02 NFactor= .8165306 dt= 2.800296E-04
+Cdsc=-1.961542E-04 Vglow=-.12 Vghigh=.12
+Cdscb=- 1.145162E-05
+EtaO= .2236274 Etab=-6.512475E-03
+Dsub=. 5180283.
*
* ROUT PAR*
+Pclm= 3.331738 Pdibll= 1.023179 Pdibl2= 6.430786E-04
+Drout= .5563746 Pscbel= 0 Pscbe2= 1E-28
+Pvag= 6.604128
+Eta-0 Litl= 2.525173E-07
+Ldd=0
30

N405551.IV, W/L=10.0/2.0, T=27

P405551.IV, W/U10.0/2.0, T=27°C, VB= 0 V
P405551.IV, W/L=10.0/2.0, T=27t'C) VD= .05 V
1 .330-3
VGS (V) =
1.20
2.16
3,12
4.08.
5,04
6,00
2.686-5
...H*"/*.. ,
2.146-5
i ••
.-•'""••"".
>::;:::""
.-•"]
•
*•
#**
VBS(V) =
0.00
-1.00 1.060-3
-2.00
•3-00 ^
1
• •""
•"".•'I'l'"
"!""''
Q
.•""-""•;
5.320-4
1.076-5
1
• .""'*
',•
^ * *
*'»'*
H
M •
2.660-4
•VI'""'
"•:-:
:;:'
2 2
• « 'B ••M'11
5360-6
(
^-
0 1
" "
0
0.0000 0
6 4.8 6
4 3
VD(V)
2 2
0 0
8 6
6 4
4 3
VG(V)
0 1
to
P405551.IV, W/L=10.0/2.0, T=27°C, VD= .05 V P405551.IV, W/U10.0/2.0, T=27°C, VB= 0 V
VGS (V) =
1.20
2.16
3.12
4,08
5.04
6.00
VBS(V) =
MtiKK'""
j|M«IM»««
::•!!"""
,
1.00-5
• «"*
-i f\_C
• "
?nn 1-7702
-2.00 ^
.
"3'°° | 1.3362
y
1.00-7
• "
.
I Do-fi
| 8.8461
••••
. . .
1.00-9
""" .,..-
:::::
_•

Vth(V)
1.55 r
VthCV)
1.33.1
15JO 20.0 25. 0.0 10.0 1SJ> 20.0 25.0
(a) (b)
Fig. 34 Threshold voltage vs. channel length (drawn) with different substraste biases,
(a) NMOS. (b) PMOS.
0.75 I—
0.0 20.0 30.0
Wdr*rm(um)
(a)
20.0 33.0
Wdmmfum)
(b)
Fig. 35 Threshold voltage vs. channel width-(drawn) with different substraste biases,
(a) NMOS. (b) PMOS.
33

2.6e4
1.3e4
Rch versus L from Channel Resistance
0.0«0
0.0 5.0 10.0 15.0
Ldrawn (um)
7.0e4
3.5e4
O.OeO
(a)
Bch versus L from Channel Resistance
20,0 25.0
Fig. 36 Effective channel length extraction with BSIMPro. (a) NMOS. (b) PMOS.
34

6 Summary
The UC Berkeley CMOS baseline is available for participating groups to submit designs for pro-
cessing, using the device parameter targets in Appendix A, the geometric design rules listed in
Appendix B and BSIM3 model for SPICE simulation. Test structures for autoprobe testing are
added for statistical evaluation. Successful runs have been completed by the baseline, cooperating
with several research groups.
The CMOS baseline continues evolution with future projects including the extension of BSIM3
model support and development of 13 (im technology.
Acknowledgments
The baseline project is supported by the following research groups in the Microlab: Berkeley Sen-
sors and Actuators Center, Profs. R. Howe, R. Muller, A. Pisano, R. White; Computer Integrated
Manufacturing, Profs. D. Hodges, CJ. Spanos; Devices and Technology, Profs. N. Cheung, C.
Hu, RK. Ko; Integrated Circuits, Prof. P. Gray; Cryoelctronics, Prof. T. Van Duzer; Materials Sci-
ence, Prof. M. Ferrari; and Microlab operating funds.
The author wishes to acknowledge the generous guidance of Prof. Costas J. Spanos and Microlab
Manager Katalin Voros.
35

References
[1] Katalin Voros and Ping K. Ko, MOS Processes in the Microfabrication Laboratory, Memoran-
dum No. UCB/ERL M87/12, Electronics Research Laboratory, University of California, Ber-
keley (10 March, 1987).
[2] David Rodriguez, Electrical Testing of a CMOS Baseline Process, Memorandum No. UCB/
ERLM94/63, Electronics Research Laboratory, University of California, Berkeley (30 August
1994).
[3] R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, New York: John
Wiley & Sons, Inc., 1986.
[4] D. K. Schroder, Semiconductor Material and Device Characterization, New York: John Wiley
& Sons, Inc., 1990.
[5] S. M. Sze, Physics of Semiconductor Devices, New York: John Wiley & Sons, Inc., 1981.
[6] Gary S. May, MOSTCAP-An MOS Transistor Characterization and Analysis Program, M.S.
research project report, Department of Electrical Engineering and Computer Sciences, Uni-
versity of California, Berkeley, 11 December 1987.
[7] Industrial Liaison Program, Research Software, 1994-2995, University of California at Berke-
ley, Electrical Engineering and Computer Sciences.
[8] BSIMProfor Windows, User's Manual, BTA Technology, Inc., February 1994.
36

Appendix A 2 Jim N-Well, Double Poly-Si and Double Metal CMOS
Parameters
vt
k' (^iCox/2)
AL (Ldrawn-Lgff)
AW (Wd^-Weff)
Yi (low VBS)
Y2(HighVBS)
S (Subthreshold Slope)
TOX
Xj (S-D)
Xw (well depth)
R-diff (sheet resistance)
Rpoly (sheet resistance)
Rwell (sheet resistance)
Rcmi-diff^m*2^)
Rcmi-poly(2^mx2^m)
lVth-field'
IS-D Breakdownl
S-D Leakage Current
(V^ = 5V, Vgs = 0V.)
Ring Oscillator (31 stages)
Process and Device Parameters Targets
Units
V
HA/V2
[im
Jim
v1/2
v1/2
mV/decade
Angstrom
[im
|im
Q/square
H/square
KQ/square
Q
Q
V
V
pA/jim
. MHz
37
N-Channel
0.74 +/- 0.08
24 +/- 4
0.4-0.8
1.2-1.8
0.4-0.65
0.15-0.2
96 +/- 4
300 +/- 30
0.3
44+/- 6
15.1+/-1.5
15 +/- 8
2.24 +/- 1
>10
>10
0.8
35
P-Channel
0.74 +/- 0.1
13+/-3
0.5-0.9
1.2-1.9
0.4-0.55
0.35-0.55
9S +/- 4
300 +/- 30
0.6
3.2
59 +/- 8
15.1 +/- 1-5
1.5 +/- 0.3
8.3 +/- 1
2.24 +/- 1
>10
>10
2

Appendix B 2 urn, N-well, Double Poly and Double Metal CMOS Design Rules
A. N-well Layer
A.1 Minimum size: 8)1
A.2 Minimum spacing: 8(1
B. Active Area
B.I Minimum size: 3)1
B.2 Minimum spacing: 3(1
B.3 N-well overlap of P-K 5)1
B.4 N-well overlap of N+: 3|l
B.5 N-well'space to N-f: 5|i
B.6 N-well space to P-1-: 5(i
B.7 N+ to P+ in substrate: 3u.
B.8 P-t- to N+ in n-well: 3(1
C. Poly 1 (Gate Poly)
C.1 Minimum size: 2)1
C.I Minimum spacing: 2(1
C.3 Spacing to active: 2)1
C.4 Gate extension: 2)1
D. Poly 2 (Capacitor Poly)
D.I Minimum size: 2)1
D.2 Minimum spacing: 2)1
D.3 Poly 1 overlap of poly 2: 1(1
E. p-plus/n-plus Implant
E.I Minimum overlap of active: 1.5)1
E.2 Minimum size: 6)1
Bl=3
Al=8
Cl=2 C4=2
E2=6
38
$D3=1

F. Contact
F.I Minimum size: 2|i
F.2 Minimum spacing (on poly): 2[i
F.3 Minimum spacing (on active): 2ji
F.4 Minimum overlap of active: 2|i
F.5 Minimum overlap of poly: 2|i
F.6 Minimum overlap of metal 1*: l|i
F.7 Minimum spacing to gate:** 2ji
G. Metal 1
H. Via
G.I Minimum size: 3 \i.
G.2 Minimum spacing: 3 p.
H.1 Minimum size: 3 jl
H.2 Minimum spacing: 3 |I
H.3 Minimum overlap of metal 1: 2|i
H.4 Minimum overlap of meta!2: 2 p.
I. Metal 2
1.1 Minimum size:
1.2 Minimum spacing:
*: 2|i for BSAC group.
**: 3|l for BSAC group.
3u.
-Fl=2 F5=2
F6=l F2=2
G2=3
Hl=3 H2=3
F4=:
Gl=3
JH4=2
iiSSBiS*?*
H3=2 11=3
12=3

Appendix C Microlab CMOS Baseline Process Log
Microlab CMOS Process
2 um, N-well, double poly-Si, double metal
0.0 Starting Wafers: 8-12 ohm-cm, p-type,
Control wafers: NWELL (p-type), NCH (p-type)
Scribe lot and wafer number on each wafer, including controls.
Piranha clean and dip in sink8.
Measure bulk resistivity (ohms-cm) of the controls on sonogage.
R =
1.0 Initial Oxidation: target = 1000 (+/- 5%) A
1.1 TCA clean furnace tube (tylan2).
1.2 Standard clean wafers:
. piranha 10 minutes, 25/1 HF dip, spin-dry.
1.3 Wet oxidation at 1000 C (SWETOXB):
. 5 min. dry..02
~9 min. wet O2 . (Checfc'the previous run result)
5 min. dry- 02
20 min. dry N2
tox=
2.0 Well Photo: Mask NWELL (chrome-df) .
(Control wafers are not included in any photoresist step)
Standard I-line process:
HMDS, spin (and soft bake), expose, post exposure bake,
develop, inspect, descum and hard bake.
3.0 Well Implant: phosphorus, 5E12/cm2,150 KeV. Include NWELL.
4.0 Well Drive-In: target xj = 3.43 um, tox = 3000 A
4.1 TCA clean furnace tube (tylan2).
4.2 Etch pattern into oxide in 5/1 BHF. Include NWELL.
40

4.3 Remove PR in O2 plasma and clean wafers in sinkS.
4.4 Standard clean wafers in" sink6, include NWELL and NCH.
4.5 Well drive at 1150 C (WELLDR):
1 hr temperature ramp from 750 C to 1150 C
4 hrs dry O2
1 hr dry N2
a) Measure oxide thickness.
tox (well)= tox (outside) =
b) Strip oxide from NWELL and NCH, measure Rs
Rs (NWELL) =
4.6 TCA clean the furnace tube after well drive-in is done.
5.0 Pad Oxidation/Nitride Deposition:
target = 300 (+60) A-SiO2 + 1000 (+100) A Si3N4
5.1 TCA clean furnace tube (tylanS). Reserve tylan9.
5.2 Remove all oxide in 5/1 BHF until wafers dewet.
5.3 Standard clean wafers. Include NWELL and NCH.
5.4 Dry oxidation at 950 C (SGATEOX):
~1 hr. dry O2
20 minutes dry N2 anneal.
Measure tox on NCH. Tox=. NCH proceed to 12.2.
5.5 Deposit 1000 (+100) A of Si3N4 immediately (SNTTC):
Include NWELL only,
approx.time = 22 min., temp.= 800 C.
Measure nitride thickness on NWELL, using tox value
obtained in 5.4. NWELL proceed to Step 10.2.
tnit =
6.0 Active Area Photo: Mask ACTV (emulsion-cf)
Standard G-line process (FirstPR).
41

7.0 Nitride Etch in laml (Process #3)
Plasma etch in laml.
Recipe: Power: Ave. etch time: Overetch:
Measure Tox on each work wafer. (2 pnt measurement).
Do not remove PR. Inspect
Measure PR thickness covering active area with as200.
PR must be >8 kA. Hard bake again for >2hrs at 120 C.
8.0 Field (P-) Implant Photo: MaskPFIELD (emulsion-cf)
Reversed NWELL mask)
Standard G-line process. (Second PR)
Well area is covered with PR. Outside well, N-channel
MOSFET active areas are covered with Si3N4 and PR.
9.0 Field (P-) Ion Implant: Bll, 70 KeV, 1.5E13/cm2.
10.0 Locos Oxidation: target = 6500 A
10.1 TCA clean furnace tube (tylan2).
10.2 Remove PR in O2 plasma and piranha clean wafers.
Standard clean wafers; dip until field area dewets.
Include NWELL.
10.3 Wet oxidation at 950 C (SWETOXB):
5 min. dry O2
4 hrs. 40 min. wet O2
5 min. dry 02
20 min. N2 anneal
Measured tox on 3 work wafers.Tox=
11.0 Nitride Removal (Include NWELL.)
11.1 Dip in 5/1 HF for 30 sec to remove thin oxide on top of Si3N4.
11.2 Etch nitride off in phosphoric acid at 145 C.
12.0 Sacrificial Oxide: target = 200 (+/- 20) A
12.1 TCA clean furnace tube (tylanS).
42

12.2 Standard clean wafers. Include NWELL and NCH.
Dip in 10:1 BHF until NWELL and NCH dewet
12.3 Dry oxidation at 950 C (SGATEOX):
30 minutes dry O2
20 minutes N2 anneal
Measure Tox on 3 wfrs. Tox=
13.0 Threshold Implant (blanket): Bll, 30 KeV, 1.7E12/cm2.
14.0 Gate Oxidation/Poly-Si Deposition:
target =300 (+/- 30) A SiO2 + 4500 (+/- 300) A poly-Si
14.1 TCA clean furnace tube (tylanS).
Reserve poly-Si deposition tube (tylanl 1).
14.2 Standard clean wafers, including NWELL, NCH and, five
Tox and one Tpolyl monitoring wafers.
14.3 Dip off sacrificial oxide in 10/1 HF
until PWELL and PCS dewet (approx. 1 min).
14.4 Dry oxidation at 950 C (SGATEOX):
~1 hrs dry O2 (Check previous run result)
20 minutes N2 anneal.
Measure 5 pnts on 3 Tox monitoring wfrs. Tox=
14.5 Immediately after oxidation deposit 4500 A of phos.doped
poly-Si (SDOPOLYH).
approx.time = 2 hr. 50 min., temp.= 610 C
Include Tpolyl, PWELL and PCH.
Tpoly 1= Measure 5 pnts on Tpoly 1, PWELL and PCH.
Tpolyl, NWELL and NCH.proceed to Step 19.2.
15.0 Gate Definition: Mask POLY -(emulsion-cf)
Standard 1-Line process.
16.0 Plasma etch poly-Si
43

16.1 Etch poly in Lam4.
16.2 Measure Tox in S/D area of each work wafer.
17.0 Capacitor Formation:
target = 800 A SiO2 on 1st poly + 4500 A 2nd poly.
17.1 TCA clean furnace tube (tylan2). Reserve tylanll.
17.2 Standard clean wafers, including NWELL and NCH, Tpolyl
and one of gate oxidation monitoring wafers as a
2nd poly monitoring wafer, Tpoly2.
Tpoly2 proceeds to Step 19.4.
From here on: only 10 sec dip in 25/1 H2O/HF after piranha.
17.3 Dry oxidation at 950 C (SDRYOXB):
56 min dry O2 (Check the previous lot result).
20 min N2 anneal.
Measure oxide thickness on poly with nanoduv:
tox(NWELL) = tox(NCH) =
NCH proceeds to 23 and NWELL proceeds to Step 26.
17.4 Second poly-Si deposition: immediately after oxidation
deposit 4500 A of phos.doped poly-Si (SDOPOLYH):
approx.time = 2 hr. 50 min, temp.= 610 C. Tpoly2=
18.0 Capacitor Photo: Mask CAP-CE (emulsion-cf),the same mask for pwell.
Standard 1-Line process.
19.0 Plasma etch poly-Si:
19.1 Etch 2nd poly in Lam4. Inspect
19.2 Measure Tox in S/D area on each work wafer.
Remove PR in 02 plasma.
44

19.3 Measure line width of 2 um gates on each work wafer.
Piranha clean wfrs in sinkS.
Dehydrate wfrs in oven for > 30 min. at 120 C.
20.0 N+ S/D Photo: MaskN-S/D (chrome-df)
Stnd I-line process. Inspect Hard bake.
21.0 N+ S/D Implant Arsenic, 160 keV, 5E15/cm2, incl. NWLL and NCH.
22.0 N+ S/D Anneal
22.1 TCA clean furnace tube (tylan?).
22.2 Remove PR in O2 plasma and piranha clean wafers
in sinkS (no dip here).
22.3 Standard clean wafers in sink6, include NCH.
22.4 Anneal in N2 at 950 C for 1 hr (N2ANNEAL).
23.0 P+ S/D Photo: MaskP-S/D (emulsion-cf)
Stnd I-line process. Inspect!
All areas are covered with PR except P-channel areas.
24.0 P+ S/D Implant: Bll at 30 keV, 5E15/cm2, include NWELL.
25.0 PSG Deposition and Densification: target = 7000 A
25.1 Remove PR in O2 plasma and piranha clean wafers
in sinkS (no dip).
25.2 Stnd clean wfrs in sink6 (10 sec dip).
Include NWELL, NCH and one PSG monitoring wafer.
45

25.3 Deposit 7000 A PSG, PH3 flow at 10.3 seem (SDOLTOD).
approx.time = 35 min. (check current dep. rate)
temp. = 450 C
25.4 Densify glass in tylan2 at 950 C, immediately.after
PSG deposition (PSGDENS). Include PSG control.
5 min dry O2,20 min wet O2,5 min dry O2.
Measure tPSG=
Etch oxide on NWELL and NCH, and measure poly
sheet resistivity on NWELL and NCH with prometrix.
25.5 Do wet oxidation dummy run afterwards to clean tube:
1 hr wet oxidation at 950 C (SWETOXB):
26.0 Contact Photo: Mask CONT (chrome-df)
Stnd 1-Line process.
.27.0 Contact Etch:
Plasma etch in Lam2.
28.0 Back side etch:
28.1 Remove PR in O2 plasma, piranha clean wfrs in sinkS (no dip).
Dehydrate wafers in oven at 120 C for >30 min.
28.2 Etch backside:
(NWELL and PWELL can be included in b), c) and d).
a) Spin PR on front side, hard bake.
b) Dip off oxide (PSG) in 5:1 BHF.
c) Etch poly-Si (poly2 thickness) in Iam4.
d) Etch oxide off in 5:1 BHF (cap. ox. thickness).
e) Etch poly-Si (polyl thickness) in Iam4.
f) Final dip in BHF until back dewets.
g) Remove PR in PRS2000, piranha clean wfrs in sinkS (no dip).
29.0 Metallization: target = 6000 A
Stnd clean wfrs and do a 30 sec. 25/1 H20/HF dip just
before metallization.
Sputter Al/2% Si on all wafers in CPA.
46

30.0 -Metal Photo: Mask METAL1-CM (emulsion-cf)
Stnd I-line process. Hard bake for >2 hrs.
31.0 Plasma etch Al in Lam3.
Remove PR in PRS2000 or technics-c. tAl=
Probe test devices.
32.0 Sintering: 400 C for 20min in-forming gas (tylanlS).
No ramping; use SINT400 program.
33.0 Testing:
2umN- andP-channel devices, capacitors and inverter
Measure the sheet resistivities of NWELL and
NCH on prometrix.
34.0 Planerization and Dielectric Film Deposition:
34J PECVD thin oxide (500 A) in technics-B:
N2O: 54.0, Silane: 14.0, Pwr: 15 W, Pressure: 360-420 mT.
~5 min. Measure Tox on .dummy wafers.
34.2 SOG coating on the Headway spinner at 3000 rpm, 20 sec.
34.3 SOG cure:
a) Oven in Y2,120 C, 30 min.
b) Oven in Rl, 200 C, 30 min.
c) Tylanl4 (SVANNEAL): 400oC, 30 min.
d) Measure Tox and refractive index on dummy wafers.
34.4 PECVD thick oxide (to total SOG & PECVD 8000 A) in technics-B:
N2O: 54.0, Silane: 14.0, Pwr 15W, Pressure: 360-420mT
Use the dep. rate obtained from 34.1 and calculate
the dep. time. Rotate .the wafers 180 degrees
at the half way point of the deposition.
Measure Tox and refractive index on dummy wafers.
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35.0 VIA Photo:
I-line 1.6 um thickness process. Descum in technics-c.
Hard bake.
36.0 Etch VIA in Iam2.
Need overetch. Test metall patterns on the wafers
with 4-pnt probe to see if the end point is reached.
37.0 Metal2 Metallization, target = 8000-9000 A
Remove PR in PRS2000 or technics-c. Rinse the wafers in
sink? and spin dry.
Sputter Al/2% Si on all wafers in CPA.
38.0 Metal Photo: Mask METAL1-CM (emulsion-cf)
G-line double thickness process. Descum in technics-c.
Hard bake for >2 hrs.
39.0 Plasma etch Al in Lam3.
Remove PR in PRS2000 or technics-c.
40.0 Sintering: 400 C for 20min in forming gas (tylanlS).
No ramping, use SINT400 program.
41.0 Testing:
Measure Metall and Metal2 contact chain.
End of Process
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