Low Frequency Noise in Advanced MOS ... - Berkeley Microlab

Low Frequency Noise in 

Advanced MOS Transistors 

Chia‐Yu Chen 

Department of Electrical Engineering 

Stanford University 

UC Berkeley EE298‐12 Solid State Technology and Device Seminar 2010‐11‐19

• CMOS scaling 

It’s ok. 

It 

IEDM 2008 short course 

Motivation 

11/19/2010 C.‐Y. Chen UCB EE298‐12 Seminar 

Low Frequency Noise becomes important! 

It’s noisy. 

2

Motivation 

• Low Frequency (LF) noise 

IC designer 

Fabrication 

Device Material 

s 

LF noise 


Physicist 

Mathematician 

3

• Introduction 

• Methodology 

• SiGe 

channel 

• Size effect 

• Conclusions 

Outline 


4


 

 

 

Why LF noise is important? 

The origin of LF noise 

CMOS scaling 


• SiGe channel 





5

S id (A 2 /Hz) 


• Noise in a MOSFET 

10 2 

10 3 

10 4 

10 5 

Frequency (Hz) 

10 6 


– White noise: thermal 

and shot noise. 

– 1/f noise: 

distribution 

in mobility. 

– G‐R noise: 

mechanism; 

case is RTN. 

noise 

certain trap 

or fluctuation 

trap/de‐trap 

one special 

Low frequency (LF) noise 

6

• Analog domain 

Sid (uA 2 Sid (uA /Hz) 

2 /Hz) 

1E-3 

1E-4 

1E-5 

1E-6 

1E-7 

1E-8 

1E-9 

Worse oxide 


1/f 

1E-10 

1 10 100 


VCO: phase noise 

Good oxide 

Up‐convert 

– LF noise is up‐converted and causes phase noise. 

– Phase noise limits channel capacity. 


Adjacent channel 

f0 

7

• Digital domain 


N. Tega, VLSI symp. 2009, p. 50‐51. 

SRAM: noise 

margin 

– LF noise increases with scaling. 

– Noise margin becomes small. 


8


 

 

 










9

• Two schools 


– Conductivity fluctuation. 

– Two schools: number 

fluctuations (Δμ). 

fluctuations 


σ=μ N eff 

(ΔN) 

and 

mobility 

10

• ΔN model: one trap 

one trap/de‐trap 

G 

s D 

N+ N+ 

A. McWhorter, Semi. 

Surf. Phys., 1957. 


Surface effect 


Random telegraph noise 

Lorentzian 

11


• ΔN model: a lot of traps 

s D 

N+ N+ 

A. McWhorter, Semi. 

Surf. Phys., 1957. 

G 

Correlated Δμ 


2.07E-006 

Id (A) 

2.06E-006 

is also induced. 

0 5 10 15 

Time (s) 

12


• ΔN model: a lot of traps 

Gate (um) 

Gate (um) 

SISPAD 2006, Y. Liu 

F=1Hz 

Channel 

1e‐3 

Depth in oxide (um) 

F=1e4Hz 

Channel 

Depth in oxide (um) 

1e‐3 

Sid(A 2 /Hz) 


1/f 


– Sum of Lorentzians: 1/f noise 

13

S nt 

( r) 

2( 

G R) 

• ΔN model: I d 

S id /I d 2 (1/Hz) 

1e‐8 


and V g 

1e‐9 

(1/Hz) 

1e‐10 

1e‐11 

Fix Vd and increase (gm/Id)2 

Vg 

Drain current (A) 

– Id: Sid/I 2 

d 

dependence 

α 

S id /I d 2 (1/Hz) 

S id /I d 2 (1/Hz) 

1E-8 

1E-9 

1E-10 

1E-11 

(gm/Id) 2 . 

– Vg: flat in weak inversion. 


0.0 0.5 1.0 1.5 

Gate Voltage (V) 

Gate voltage (V) 

14

• Δμ 

model 

– Bulk phonon scattering 

Source 

– Empirical equation 

T‐ED 1994, F. N. Hooge 


Gate 

P+ P+ 

N-type Si substrate 

S q 

 

I WLQ f 

Id H 

2 

d i 

Drain 


S id (uA 2 /Hz) 

1E-3 

1E-4 

1E-5 

Bulk effect 

1/f 

1 10 

Phonon Si bulk 

Hooge mobility fluc. 


15 

100

S nt 

( r) 

2( 

G R) 

S id /I d 2 (1/Hz) 

• Δμ 

1e‐8 

1e‐9 

model: I d 

1e‐10 

1e‐11 


and V g 

S q 

 

I WLQ f 

Id H 

2 

d i 


– Id: Sid /I d 2 

– Vg: Sid/I 2 

d 

α 

dependence 

1/Id. S Sid /I 2 

id /I 2 

dd(1/Hz) (1/Hz) 

1E-7 

1E-8 

1E-9 

1E-10 

1E-11 

increases when V g 


-0.5 0.0 0.5 1.0 1.5 2.0 



decreases. 

16

S id /I d 2 (A 2 /Hz) 

• ΔN or Δμ? 

G. Ghibaudo, Noise in 

Devices and Circuits, 2003. 



Sid /I 2 

S d (1/Hz) 

id /I 2 

d (A2 /Hz) 

– Different trend in I d 

1E-7 

1E-8 

1E-9 

1E-10 

1E-11 

and V g 


Δμ 

Fix Vd and increase Vg 

ΔN 

0.0 0.5 1.0 1.5 2.0 

Gate Voltage voltage (V) (V) 

dependence. 

17


 

 

 



CMOS Scaling 







18


Size: 

Larger variability 

– CMOS scaling: provide new opportunity to optimize LF noise. 


19



 

 

 

Overview 

TCAD simulations 

Noise characterization 






20

Overview 

TCAD 

simulations 

Noise 

characterization 


Explain low 

frequency noise 

mechanism 

21



 

 

 

Overview 

TCAD simulation 







22


S =S id_total id_ ΔN 

– Total noise is the sum of ΔN and Δμ. 

– No correlation. 


+S id_ Δμ 

23


• Impedance field method (IMF) 

Vs 

W. Shockley, Quantum 

Theory of Atoms, 

Molecules and Solid State, 

1966, pp. 537–563. 

Vg 

Injection 

current 


Voltage 

fluct. at 

drain 

Vd 

24


• Impedance field method (IFM) 

Source 

Gate 

oxide 

Tride Saturation 

Pinch‐off 

IFM: linear No effect 



25

• ΔN model 


oxide 

channel 

G‐R 

– Noise source is inside oxide. 

– A rate equation to correlate oxide traps and channel 

carriers and then apply IMF to calculate Sid. 11/19/2010 C.‐Y. Chen UCB EE298‐12 Seminar 

drain 

26

2 

( 1 

n 2 D / 

c 0 ) 

• Δμ 

model 


S q 

Id 

2 H 

d i 

~1e-5 for Si material 

 

I WLQ f 

Extract from TCAD 

– Extract parameters from TCAD simulations such as Qi. 


IEEE T‐ED 2008, C.‐Y. Chen 

27


• The origin of LF noise 


 

 

 

Overview 

TCAD simulations 







28

• Basic schematic 

HP 4156 


Offset 

current 

DUT 

SR 570 

Signal 

analyzer 

A. Blaum, Agilent document, 2000. 

– Offset current removes the DC component at the input. 

– SR570 is used to drive high impedance loads and input impedance 

of signal analyzer should be high. 


29


• Measurement bench 

Wafer (DUT) 

SR 570 


Gate 

Source 

Bulk 

Cascade probe station HP4156 


SR760 FFT spectrum analyzer 

30




 

 

 

Device schematic 

Gate bias 

Body bias 





31

• Si/SiGe/Si p‐HFET 

Si 

SiGe 

Si 

– Two channels: 

channel. 


Parasitic surface channel 

SiGe 

Gate 

SiO 2 

SiGe buried channel 

Source Lg=1um Drain 

Bulk 

buried 

Body 

Si/SiGe/Si p-MOSFET 

channel 


and 

L/W=1um/10um 

oxide thickness=6nm 

Devices from Panasonic 

parasitic 

surface 

32

• Advantage 


1E-22 

1 10 100 1000 10000 

– Improve LF noise: (1) longer tunneling distance and (2) smaller 

Coulomb interaction. 


1E-18 

1E-19 

1E-20 

1E-21 


W/L=10um/1um 

Vd=-0.5V 

|Vg|-|Vth|=0.3V 


Si: TCAD 

Si: meas. 

Si/SiGe/Si: TCAD 

Si/SiGe/Si: meas. 

33




 

 

 


Gate bias 

Body bias 





34

• Dual‐channel behavior 

1E-17 

1E-18 

1E-19 

Sid (A 2 /Hz) 

W/L=10um/1um 

Vd=-0.5V 

Vov=2V 

Si: TCAD 

Si: meas. 



1E-20 

1 10 100 1000 


Charge Density (C/m 2 ) 

0.006 

0.004 

0.002 

Gate bias 

Si/SiGe/Si p-HMOS 

Surf. charge 

Buried charge 

Vd=-0.1V 

0.000 

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 


1E-22 

1 10 100 1000 10000 

– When buried channel dominant LF noise is reduced. 


1E-18 

1E-19 

1E-20 

1E-21 

Sid (A 2 /Hz) 

W/L=10um/1um 

Vd=-0.5V 

|Vg|-|Vth|=0.3V 


Si: TCAD 

Si: meas. 



35

• Vg dependence 

ΔN 

S id /I d 2 (1/Hz) 

1E-7 

1E-8 

1E-9 

1E-10 

1E-11 

Gate bias 

SiGe p-HMOS 

Number fluc. 

Mobility fluc. 

Total noise 

Measurements 

Vd=-0.1V 

1E-12 

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 


– Weak inversion: Δμ 

– Medium/strong inversion: ΔN 


Δμ 

ΔN 

36

• I d 

dependence 

S id /I d 2 (1/Hz) 

10 -7 

10 -8 

10 -9 

10 -10 

10 -11 

10 -12 

10 -13 

10 -14 

10 -15 

10 -16 

Δμ 

Gate bias 

1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 

Drain Currrent (A) 

– Weak inversion: Δμ 


V d =-0.1V 

ΔN 

– Medium/strong inversion: ΔN 


10 7 

10 6 

10 5 

10 4 

10 3 

10 2 

10 1 

10 0 

10 -1 

10 -2 

(g m /Id) 2 (V -2 ) 

37




 

 

 


Gate bias 

Body bias 





38

• SiGe p‐HFET 


1E-20 

1E-21 

1E-22 

1E-23 

TCAD 

Vb =-0.4V 

V b =-0.2V 

V b =0V 

V b =0.2V 

Mea. 

Body bias 

V b =-0.4V 

V b =-0.2V 

V b =0V 

V b =0.2V 


Vov=-0.3V 

Vd=-0.5V 

10 100 1000 


reverse 

forward 

SISPAD 2007, C.‐Y. Chen 

– LF noise in SiGe p‐HFET has strong body bias dependence. 


39


Surf. Buried 

Hole density (cm -2 ) 

1E15 

1E14 

forward 

Body bias 

Vov=-0.3V 

Vd=-0.5V 

Si cap layer 

SiGe channel 

1E13 

-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 

Body bias (V) 



reverse 

Surf. Buried 

– Body bias changes carrier distribution in dual channels 


T‐ED 2008, C.‐Y. Chen 

40


less noisy 


1E-20 

1E-21 


Vov=-0.3V 

Vd=-0.5V 

Body bias 

Si cap layer hole density 

Simulated Sid 

Measured Sid 

1E-22 

-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 

forward 

Body bias (V) 

1E16 

1E15 

1E14 

reverse 

Surface carrier density (cm -2 ) 

– FL noise is mainly from surface channel. 


more noisy 

T‐ED 2008, C.‐Y. Chen 

41

• Si p‐FET 


1E-19 

1E-20 

1E-21 

Si pMOS 

Vov=-0.3V 

Vd=-0.5V 

Body bias 

Mea. 

Vb =-0.4V 

V b =-0.2V 

V b =0V 

V b =0.2V 

TCAD 

Vb =-0.4V 

V b =-0.2V 

V b =0V 

V b =0.2V 

10 100 1000 


– Si p‐MOS does not show body bias dependence. 


SISPAD 2007, C.‐Y. Chen 

reverse 

forward 

42





 

 

 


Mechanism 

Gate bias 




43


• Scaled MOSFETs (small gate area) 

Cross view Top view 

α 

L/W=40nm/70nm 

oxide thickness~2.5nm 

Devices from G‐foundries 

– Only a few traps are involved. 

– ΔN predicts RTN; Δμ 


shows 1/f noise. 

44





 

 

 


Mechanism 

Gate bias 




45

• Ig‐ 

/ Id‐RTN 

A few trap/de‐trap 

G 

s D 

N+ N+ 

– Two types: Ig‐RTN 

Mechanism 

Ig 

and Id‐RTN. 


Time 

Id 

Time 

46

Electron mobility (cm 2 /Vs) 

• Where are traps? 

320 

280 

240 

200 

160 

120 

Mechanism 

High-k metal gate nMOSFET 

(HfO 2 /TiN) 

0.4 0.8 1.2 1.6 2.0 2.4 

Interfacial layer thickness (nm) 

– Traps should be inside high‐κ 

gate 

oxide. 


x x 

x 

HfO 2 

SiON 

channel 

47

• Trap/de‐trap 

Et 

– Capture: V th 

– Emission: 

V th 

Mechanism 

Ef 

I g (A) 

I d (A) 

7.40E-012 

7.20E-012 

7.00E-012 

1.60E-006 

1.58E-006 

1.56E-006 

and TAT increase I d 

and TAT decrease I d 


charge trap 

(capture) 

Track each other 

charge de-trap 

(emission) 

de-trapped 

state 

trapped 

state 

0 10 20 30 

and I g 

Time (s) 

and I g 

48

• PBTI and RTN 

I d (A) or I g (A) 

1E-5 

1E-7 

1E-9 

1E-11 

1E-13 

Mechanism 

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 

V g (V) 

I g 

– Consistent with RTN results. 


I d 

Before stress 

Positive stress 

Negative stress 

49





 

 

 


Mechanism 

Gate bias 




50

Ig (A) 

• Ig‐RTN 6.4x10 -11 

6.0x10 -11 

5.6x10 -11 

5.2x10 -11 

3.6x10 -11 

3.2x10 -11 

2.0x10 -11 

1.8x10 -11 

1.6x10 -11 

– V g 

0 5 10 15 20 25 

Time (s) 

Gate bias 

Vg=1V 

Vg=0.9V 

Vg=0.8V 

increases: Time in high‐I g 


Et 

state increases. 

Ef 

51

Id (A) 

• Id‐RTN: Low Vg 

2.30E-009 

2.25E-009 

2.20E-009 

2.15E-009 

2.10E-009 

2.05E-009 

Vd=10mV Vg=0.2V 

150 155 160 165 170 

Time (s) 

Gate bias 

Sid (A 2 /Hz) 

1E-19 

1E-20 

1E-21 

1E-22 

1E-23 

– Measurement still shows 1/f noise; Δμ 


Vg=0.2V 

Vd=20mV 

Scaled nMOSFET 

L=50nm 

W=70nm 

1E-24 

0.01 0.1 1 10 


1/f 

model is dominant. 

52

Id (A) 

Gate bias 

• Id‐RTN: High gm bias condition 

4.80E-007 

4.75E-007 

4.70E-007 

4.65E-007 

Vd=10mV Vg=570mV 

4.60E-007 

20 25 30 35 

Time (s) 

Sid (A 2 /Hz) 

1E-15 

1E-16 

1E-17 

1E-18 

1E-19 

1E-20 

– RTN and Lorentzian shape are observed 


Vd=10mV 

Vg=570mV 


L=50nm 

W=70nm 

0.1 1 10 


1/f 2 

in high gm region. 

53

Id(A) 

• Id‐RTN: High Vg 

8.42E-007 

8.40E-007 

8.38E-007 

8.36E-007 

8.34E-007 

8.32E-007 

8.30E-007 

8.28E-007 

8.26E-007 

Vd=10mV Vg=750mV 

0 10 20 30 40 

Time (s) 

Gate bias 

Sid (A 2 /Hz) 

1E-16 

1E-17 

1E-18 

1E-19 

1E-20 

Vd=10mV 

Vg=750mV 


L=50nm 

W=70nm 

0.1 1 10 

– 1/f noise is shown in a very scaled MOSFET: Δμ 



1/f 

is dominant. 

54

• Id‐RTN: summary 

1/f 

gm (1/ohm) 

2.0x10 -6 

1.6x10 -6 

1.2x10 -6 

8.0x10 -7 

4.0x10 -7 

0.0 

Δμ 

Gate bias 

Vd=10mV 

Scaled nMOS 

L/W=50nm/70nm 

-0.4 0.0 0.4 0.8 1.2 

Vg (V) 

ΔN 

Δμ 

RTN 

1/f 

– RTN should be considered especially in high gm region. 


55

• Id‐RTN: summary 

Sid/Id 2 

1/f 

gm (1/ohm) 

2.0x10 -6 

1.6x10 -6 

1.2x10 -6 

8.0x10 -7 

4.0x10 -7 

Freq 

0.0 

Δμ 

Gate bias 

Vd=10mV 

Scaled nMOS 

L/W=50nm/70nm 

-0.4 0.0 0.4 0.8 1.2 

Vg (V) 

ΔN 

Δμ 

– RTN should be considered especially in high gm region. 


Sid/Id 2 

1/f 

Lorentzian 

Sid/Id 2 

1/f 

Freq 

56 

Freq


• The origin of LF noise 





 

 

 

Summary 

Contributions 

Future work 



57

Summary 

Bias SiGe H‐MOS (Lg~1um) Scaled MOS (Lg~40nm) 

Weak inversion Δμ model is dominant. Δμ model is dominant. 

High gm region (~ Vdd/2) ΔN model is important; 

LF noise is mostly surface 

effect. 

High Vg condition 

ΔN is dominant in our 

device, but in general it 

can be technology 

dependence. 


ΔN model becomes 

important; RTN should be 

considered. 

Δμ model is dominant 

58

The origin of LF noise: (1) 

Methodology: 

Summary 

ΔN model and (2) 

Δμ 

model. 

TCAD simulations and noise measurements 

SiGe channel: Dual‐channel is 

frequency noise performance. 

important 

to 

explain 

the 

low 

Size effect: Ig‐RTN is directly related to physical trapping or de‐ 

trapping and the Id‐RTN reflects sensitivity to charge trapping 

as determined by gm. CMOS scaling: provides a new opportunity for LF noise study. 


59

Contributions 

Detailed LF noise mechanisms in SiGe p‐HFET are proposed. 

LF noise mechanisms in scaled MOSFETs are 

analyzed. 

measured 

and 

Other parts: (1) LF noise mechanisms in high‐κ MOSFET, (2) 

A LF noise compact model in SiGe p‐HFET, (3) linearity of 

asymmetric channel doping for LDMOS, (4) linearity in GaN 

HEMTs, and (5) asymmetric FET scaling. 


60

Future work 

Rethink “device noise” 

“distortion” and 

“reliability” 


61

Publications 

[1] C.‐Y. Chen, Q. Ran, H.‐J. Cho, A. Kerber, Y. Liu, M.‐R. Lin, and R. W. Dutton, IRPS, 2011. 

[2] C.‐Y. Chen, C.‐C. Wang, Y. Ye, Y. Liu, Y. Cao, and R. W. Dutton, SASIMI, 2010. 

[3] C.‐Y. Chen, O. Tornblad, R. W. Dutton, IEEE Trans. on Microwave Theory and Techniques, 

Dec. 2009. 

[4] C.‐Y. Chen and R. W. Dutton, IEEE Design & Test of Computers, 2009. 

[5] C.‐Y. Chen, Y. Liu, J. Kim, R. W. Dutton, SISPAD 2009, Sept. 2009. 

[6] C.‐Y. Chen, O. Tornblad, R. W. Dutton, IEEE MTT‐S International Microwave Symposium 

Dig. (IMS), pp. 601‐604, 2009. 

[7] C.‐Y. Chen, Y. Liu, R. W. Dutton, J. Sato‐Iwanaga, A. Inoue, H. Sorada, SASIMI 2009, 

Sapporo, Japan, pp. 405‐409, March 2009. 

[8] C.‐Y. Chen, Y. Liu, R. W. Dutton, J. Sato‐Iwanaga, A. Inoue, H. Sorada, IEEE Trans. 

Electron Devices, July, 2008. 

[9] J. Kim, C.‐Y. Chen and R. W. Dutton, Journal of Computational Electronics, Jan. 2008. 

[10] C.‐Y. Chen, Y. Liu, R. W. Dutton, J. Sato‐Iwanaga, A. Inoue, H. Sorada, SASIMI, Sapporo, 

Japan, pp. 238‐241, Oct. 2007. 

[11] C.‐Y. Chen, Y. Liu, R. W. Dutton, J. Sato‐Iwanaga, A. Inoue, H. Sorada, Workshop on 

Compact Modeling (WCM) 2007, San Jose, USA, March 2007. 

[12] J. Kim, C.‐Y. Chen, R. W. Dutton, SISPAD, Nov. 2007. 

[13] J. Kim, C.‐Y. Chen, R. W. Dutton, Proc. of 12th International Workshop on 

Computational Electronics (IWCE), Oct. 2007. 


62

Backup: Linearity analysis of lateral channel 

doping in RF power MOSFETs 

Chia‐Yu Chen 

Department of Electrical Engineering 

Stanford University 

UC Berkeley EE298‐12 Solid State Technology and Device Seminar 2010‐11‐19


• Quasi‐1D structure 

• Realistic LDMOS structure 


Slide 64 

Backup: Outline

Linearity: 

Slide 65 

Backup: Introduction (1 of 2) 

ω ω 

Low distortion is one of the most important concerns for wireless 

communication systems. 

Analysis of the distortion generated by the device itself has been fairly limited.

Harmonic balance device simulations: 

A unique harmonic balance (HB) device simulator with the capability of 

including external circuitry is used. 

In the HB simulations, variations in device parameters are directly reflected 

in the final large signal RF performance. 

Slide 66 

Backup: Introduction (2 of 2)

Channel doping (cm -3 ) 

1E18 

1E17 

1E16 

Slide 67 

Backup: Quasi‐1D structure (1 of 3) 

Device schematic: 

uniform 8e16 cm -3 

uniform 2e17 cm -3 

char. length 0.2um 


Gate 

Source Graded 

channel 

doping 


0.0 0.1 0.2 0.3 0.4 0.5 

Lateral location (um) 

0.5um gate length, 30nm oxide 

thickness. 

Avoid 2D-effects. 

Very high source and drain 

dopings to avoid compensation 

effects at source and drain 

junctions. 

4 cases: 2 uniform doping and 2 

laterally graded. 

Test circuit consisting of bias 

feeds and blocking capacitors on 

input and output.

Gm 3 /Gm 

0 

Slide 68 


gm3/gm: 

1.5 2.0 2.5 3.0 3.5 


uniform 8e16cm -3 




Different gm3/gm magnitudes for 

different cases. 

Devices were biased at gm3/gm 

minima, close to overall best 

linearity. 

IM3dBc 

-25 

-30 

-35 

-40 

-45 

-50 

-55 

-60 

-65 

IM3: 





Freq.=10MHz 

-1.5 -1.0 -0.5 0.0 

Log 10 (V in ) 

First data point correlates to 

magnitude of gm3/gm minima. 

Shorter char. length / lower 

uniform doping: higher IM3 at 

low input power lower IM3 at 

high input power.

Lateral electrical field (V/cm) 

4x10 5 

3x10 5 

2x10 5 

1x10 5 

0 

Slide 69 


Field distribution: 

unifrom 8e16cm -3 




Vg at gm3/gm min. 

Vd: 2.0V 

0.0 0.1 0.2 0.3 0.4 0.5 

Lateral channel position (um) 

Graded cases more uniform 

field. 

Smaller uniform doping more 

uniform field. 

Uniform lateral field better 

linearity at higher power.

Lateral channel doping (cm -3 ) 

1E20 

1E19 

1E18 

1E17 

1E16 

1E15 

1E14 

Slide 70 

Backup: Realistic LDMOS (1 of 4) 

Device schematic (based on Infineon 7 th generation 

design): 





0.4 0.6 0.8 

Lateral channel location (um) 

Two different lightly doped drain 

regions: optimize on-resistance and 

breakdown voltage. 

Source doping and lightly doped 

drain kept the same for all cases. 

Four different lateral grading cases in 

channel, defined through analytical 

expressions.

Gm3/Gm1 

1.5 

1.0 

0.5 

0.0 

-0.5 

-1.0 

-1.5 

-2.0 

Slide 71 


gm3/gm: 





6.0 6.3 6.6 6.9 7.2 7.5 


Bias-point at gm3/gm minima. 

Test circuitry: 

Circuitry with internal and external 

matching and bias. 

Infineon product PTF210451.

IM3dBc 

Slide 72 

-30 

-40 

-50 

-60 


IM3 at 2.14GHz: 





Freq. = 2.14GHz 

0.0 0.5 

Log10(Vin) 

IM3dBc 

-30 

-40 

-50 






-60 

20 25 30 35 40 

Effect of graded doping is significant the nonlinearities in capacitances will 

not swamp the studied effects at high frequency. 

More graded channel profile shows better linearity in the intermediate power 

regime. 

IM1

IM3dBc 

-30 

-40 

-50 

-60 

20 25 30 35 

Slide 73 


Vgs shifts from gm3/gm: 

char. 0.0525um; shift 50mv 

char. 0.0925um; shift -30mv 

char. 0.0525um; shift 0mv 

char. 0.0925um; shift -100mv 


IM1 

Vgs shifts from gm3/gm 

minima IM3 change is 

quite sensitive. 

Different device designs 

give different IM3 that 

cannot be compensated for 

by simply changing Vgs bias 

(Idq setting).

• A graded channel has better linearity for intermediate to 

high powers. By contrast, for increased back‐off, the 

situation is reversed. 

• Nonlinearities in intrinsic capacitances will not swamp the 

effect of graded channel doping at high frequency. 

• The effect of graded channel doping cannot be fully 

compensated for by adjusting the Idq bias point. 

• The analysis lays ground‐work for RF device optimization for 

improved linearity. 

Slide 74 

Backup: Conclusions

Drain current, log scale (A/um) 

1E-4 

1E-5 

1E-6 

1E-7 

1E-8 

1E-9 

1E-10 

1E-11 

1E-12 

0.0 

0 1 2 3 4 

Slide 75 

Backup: Additional information (1 of 4) 

Quasi-1D structure: IdVgs 





Vd=2.0V 


2.0x10 -4 

1.8x10 -4 

1.6x10 -4 

1.4x10 -4 

1.2x10 -4 

1.0x10 -4 

8.0x10 -5 

6.0x10 -5 

4.0x10 -5 

2.0x10 -5 

Drain current, linear scale (A/um) 

Gm 3 /Gm 

0 

1.5 2.0 2.5 3.0 3.5 






Clearly different gm3/gm magnitudes for different cases. 

Shorter characteristic length and lower doping give larger gm3/gm 

magnitudes. 

Devices were biased at gm3/gm minima, close to overall best 

linearity for many applications.

Gm3/Gm 

Quasi-1D structure: velocity saturation: 

0.0 

-0.5 

-1.0 

-1.5 

-2.0 

Slide 76 


Uniform doping 2e17cm -3 

2.6 2.8 3.0 3.2 3.4 3.6 


w/ Vsat model 

w/o Vsat model 

IM3dBc 

When Vsat model is not included: 

-30 

-40 

-50 

-60 

-70 

Uniform doping 2e17cm -3 

-80 

-25 -20 -15 -10 -5 0 5 10 

IM1 

w/ Vsat model 

w/o Vsat model 

1. gm3/gm shifts to a smaller magnitude. 

2. IM3 is much lower, both initially and for high powers.

IM3dBc 

-30 

-35 

-40 

-45 

-50 

-55 

-60 

-65 

Slide 77 


Realistic LDMOS: IM3 at 10MHz 

Freq.=10MHz 





-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 

Log10(Vin) 

IM3dBc 

-30 

-35 

-40 

-45 

-50 

-55 

-60 

-65 

Freq.=10MHz 





-10 -5 0 5 10 15 20 

First, separate nonlinearities in static IV from capacitive effects 

low freq. 10MHz. 

More graded channel profile shows better linearity in intermediate 

power regime. 

IM1

IM3dBc 

-20 

-30 

-40 

-50 

-60 

-70 

-80 

-90 

Slide 78 


Realistic LDMOS: two sweet spots 

Shift -50mV from gm3/gm min. 

gm3/gm min. 

-10 -5 0 5 10 15 20 

IM1 

At high power, the compressing 

non-linearity along the load-line 

will dominate; the curves merge. 

Lower Vgs two sweet-spots 

appear. 

Ids (A) 

Vds (V)

Backup: GaN GaN HEMT HEMT structure structure 

Lg=0.5um 

11/23/2010 GaN HEMT project 79

Id (A/um) 

0.0012 

0.0010 

0.0008 

0.0006 

0.0004 

0.0002 

Backup: Id‐Vgs, GaN HEMT 

TCAD simulation results 

w/o Hydrodynamics 

w/ Hydrodynamics 

0.0000 

-7 -6 -5 -4 -3 -2 -1 0 1 

Vg (V) 

Id (A/um) 

1E-3 

1E-4 

1E-5 

1E-6 

1E-7 



-5 -4 -3 -2 -1 0 1 

Vg (V) 

11/23/2010 GaN HEMT project 

80

Gm3/Gm1 

Backup: Gm3/Gm1, GaN HEMT 

40 

20 

0 

-20 



Gm3/Gm1 min.:Vg=-4.9047V 

-5 -4 -3 -2 

Vg (V) 

11/23/2010 GaN HEMT project 

81

Id(A) 

Backup: Linearity, GaN HEMT 

1E-8 

1E-10 

1E-12 

1E-14 

1E-16 

Id1 at f1 

Id3 at 2f1-f2 

GaN HEMT 

Vd=28V 

Vg=-4.91V (Gm3/Gm1 min.) 

0.01 0.1 

Vg(V) 

11/23/2010 GaN HEMT project 82

• ΔN model 

ΔN 

Backup: The origin of LF noise 

one trap RTN 

time: 

freq.: 

a lot of traps 1/f noise 


Id 

Sid/Id 2 

Time 

Freq 

time: 

freq.: 

Id 

Sid/Id 2 

83 

Time 

Freq

• Statistical results 

Backup: Statistics 


About 12% MOSFETs 

RTN: 9% Ig‐RTN, 2% 

and 1% ‐RTN. 

Ig‐/Id I d 

show 

‐RTN, 

The statistical results are from 

1000 devices with the same 

technology and structures. 

84

Ig (A) 

• Ig‐RTN 6.4x10 -11 

6.0x10 -11 

5.6x10 -11 

5.2x10 -11 

3.6x10 -11 

3.2x10 -11 

2.0x10 -11 

1.8x10 -11 

1.6x10 -11 

– V g 

Backup: Gate bias 

0 5 10 15 20 25 

Time (s) 

Vg=1V 

Vg=0.9V 

Vg=0.8V 

increases: Time in high‐I g 

 

10 

1 

0.1 

0.01 


0.6 0.7 0.8 0.9 1.0 1.1 1.2 

state increases. 

Vg (V) 

Device 1 

Device 2 

Device 3 

Device 4 

85

Backup: TCAD 

• Id‐RTN: High gm bias condition 

Trap/de-trap 

– TCAD simulations confirm the origin of RTN can be from one‐ 

trap/de‐trap. 


86

Portable electronics 

Ultra‐low power circuits 

 

Backup: Motivation 

Transistor reliability 

Noise: key issue 

development. 

Integrated sensors 

Device Noise 

for 

the 

future 

SRAM yield 

Bio‐implant system 

Bio/silicon interfaces 

electronic 

system 

11/09/2010 C.‐Y. Chen UCB seminar 

87

U-shape 

Energy (eV) 

Backup: Trap distribution (1 of 2) 

L/H H/L 

Space (um) 

– Space: from gate to Si can be low-high or high-low. 

– Energy: distribution is a U-shape in log-scale. 

R. Jayaraman et al. IEEE T-ED, vol.36, no. 9, pp. 1773-1782, Sept., 1989. 

H. Wong et al. IEEE T-ED, vol.37 no. 7, pp. 1743-1749, July, 1990. 


88

• V g 

flat 

Backup: Trap distribution (2 of 2) 

dependence 

– V g dependence shows flat region in weak inversion regime. 

– In the U-shape distribution Vg dependence is less sensitive 

compared with uniform distribution. 

K. K. Hung et al. IEEE T-ED, vol.37, no. 5, pp. 1323-1333, May, 1990. 

Y. Liu et al. SISPAD 2006, pp. 99-102, 2006. 

∝ 

1/V ov 2 


89

Backup: Numerical method (1 of 2) 

– Physical model 

– Impedance field method (IMF) 

A k 

 

r Current fluctuatio n at kth electrode 

 

Injected current at r in the device 

2 ) 

S A dv 

 

( s 

r S r [5] A. McWhorter, Semiconductor Surface Physics, PA, Univ. Pennsylvania Press,1957, pp. 207-208. 

[6] W. Shockley et al., Quantum Theory of Atoms, Molecules and Solid State, NY: Academic, 1966, pp. 537-563. 


in 

90

Backup: Numerical method (2 of 2) 

• Hooge mobility fluctuation (Δμ 

– Bulk phonon scattering 

– Empirical equation 

– Numerical approach: Post process 

model) 

Hooge model is empirical the post process with simulated 

parameters/reasonable α H is used. 

[7] F. N. Hooge, IEEE T-ED, vol.41, no. 11, pp. 1926-1935, Nov., 1994. 


91

Backup: Unified model (1 of 4) 

The fluctuating oxide charge density △Q ox is equivalent to a 

variation in the flat-band voltage 

The fluctuation in the drain current yields 

Fluctuation of Num. Fluctuation of correlated mobility 

The first term in the parentheses is due to fluctuating number of 

inversion carriers and the second term to correlated mobility 

fluctuations. 


92


The power spectral density of the flat-band voltage fluctuations 

is calculated by summing the contributions from all traps in the 

gate oxide. 

Fermi‐Dirac distribution 

z 

y 

Semiconductor 


x 

93


The product f(E)(1-f(E)) is sharply peaked around the quasi- 

Fermi level 

If the Fermi-level is far above or below the trap level, the trap 

will be filled or empty. 

f(E) 1-f(E) 

Fluctuations 


All empty 

All filled 

94


The trapping time constant 

(quantum tunneling) 

Tunneling attenuation length 


Lorentzian spectrum 

95

• Numerical approach 

High-κ 

SiON 

j 

Different affinities and tunneling are 

considered 

Si 

Backup: High‐κ 

[9] Y. Liu et al. SISPAD 2006, pp. 99-102, 2006. 


1/γ 

f=1Hz 

f=1e4Hz 

SiO 2 : 1×10 -8 cm 

HfO 2 : 2.1×10 -8 cm

Backup: Noise scaling (1 of 2) 

• Scaling trend: general trend 

– SiO 2 trap density is much smaller than that of HfO 2 . 

– 1/f noise increases much faster than the thermal noise 

when size scales down. 


97

Backup: Noise scaling (2 of 2) 

• Scaling trend: traps at gate edge 

– High trap density in the gate edge region. 

– In the scaled devices traps in the gate edge becomes 

important so S id /I d 2 increases significantly. 

[14] Y. Yasuda et al., IEEE T-ED, vol.55, no. 1, pp. 417-422, Jan., 2008. 


98

Backup: Halo doping 

– Halo doping profiles suppress the short channel effect. 

– The same amount of electrons greater Δ 

I d in halo. 

– Reduced inversion carrier density in the halo regions. 

[8] Y. Liu et al. SISPAD 2006, pp. 99-102, 2006. 


99

Backup: Metal gate 

Poly SiGe 

High-κ (TiN) 

– The lowering of the 1/f noise: observed in the strong inversion 

regime. 

– Traps and charges at the gate dielectric interface: better 

screened by a metal gatealleviate remote phonon scattering. 

[15] E. Simoen et al., IEEE T-ED, vol.40, pp. 2054-2059, 1993. 


+ 

- 

- 

+ 

100

Backup: SiGe FET (1 of 2) 

• Dual channel behavior 

– Surface and buried channels have 

different Coulomb interactions. 

– Both channels also have different 

material quality. 

1E-20 

1E-21 

1E-22 

1E-23 

[16] C.-Y. Chen et al., IEEE T-ED, vol.55, no.7, pp. 1741-1748, 2008. 




Vd= -0.1V 

n 3-D 

w/o layer dependence 

This work 

Measurements 

-2.0 -1.5 -1.0 -0.5 0.0 


101

• Compact model 

Surface channel Buried channel 

Case 1: low Vg 

Vth_buried 

Vth_surf 

Case 3: High Vg 

Vg 

Si 

Case 2: Medium Vg 

Thin body MOS 

SiGe 

Si 

Backup: SiGe FET (2 of 2) 

SiGe 

Si 

SiGe 

Si 

SiGe 

Si 

Vth_surf 

1E-10 

1E-11 

1E-12 

-2.0 -1.5 -1.0 -0.5 0.0 0.5 

– Physics based compact model can simulate dual-channel 

behavior for SiGe FETs. 

S id /I d 2 (1/Hz) 

1E-5 

1E-6 

1E-7 

1E-8 

1E-9 

1E-3 

1E-4 

1E-5 

1E-6 

1E-7 

1E-8 


Sid (A 2 /Hz) 

10 7 


Vd=-0.1V 

TCAD 

Proposed model 

Measurements 

Vg(V) 


Si p-MOS 

10 8 


10 9 

102

Backup: Random Telegraph Noise (1 of 2) 

• Exponential tail in RTN 

– The slope of Vth instability shows an exponential tail. 

– The slope increases with technology scaling. 

[18] A. Ghetti et al., IEEE T-ED, vol.56, no.8, pp. 1746-1752, 2009. 


103

Backup: Random Telegraph Noise (2 of 2) 

• Body bias dependence: explain 

– RTN: channel/gate dielectrics system in dynamic equilibrium. 

– NBTI relaxation: perturbed system returning to the equilibrium. 


104

• Switched MOS 

Backup: Switched bias 

– Large switch in gate can reduce 1/f noise. 

[19] A. P. Wel et al., IEEE JSSC, vol.42, no.3, pp. 540-550, 2007. 


105

Backup: Temperature effect 

• RTN 

 

1/f noise 

[20] M. J. Deen et al. AIR conf. vol. 282, pp. 165-188, 1992. 


106

Backup: 1/f noise characterization (1 of 4) 

SR 570 settings 

– The sensitivity is 2uA/V 

– High bandwidth mode is used. 

Noise floor ~ 10 -10 Amps/rootHz Bandwidth ~ 1MHz 


107


SR 760 settings 

– Impedance ~ 1MΩ, 15pF 

– Bandwidth: DC to 100kHz 

– The bandwidth of noise measurement is limited by 

SR760. 

– Good for very low frequency measurements. 


108


HP4396A 

– Impedance ~ 50Ω. 

– Bandwidth: 2Hz to 1.8GHz 

– Easy interface and high 

resolution. 


Active probe HP41800A 

– Impedance ~ 1MΩ. 

– Bandwidth: 5Hz to 500MHz 

– Convert high impedance to 50 Ω. 

109


On‐package measurements 


110

Low Frequency Noise in Advanced MOS ... - Berkeley Microlab

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