Design of LCOS Microdisplay Backplanes for Projection Applications

Chapter 2: Constraints from lcos technology CH2 - 45
With full custom design, the layout is constructed through manual placement of
devices, interconnections (arrow 2). It is needless 3 to say that even for moderately
complex circuits, the layout job quickly becomes tedious. Three different (Cadence)
tools speed up the layout job, especially for circuits involving large amounts of
repetition. A first tool is the 'structure compiler’, which helps generating aligned
arrays of cells through parameterization of the arrays. The second tool comes with
parameterized cells – the so-called pCells. Pcells represent programmable layout
blocks. The third tool is the Skill ® language interpreter that allows to access, to
modify and to create data directly in the design database. Section 5.3 gives scores of
examples. Yet another tool is the verification software; it can automatically generate
some (parts of) mask layouts from the data for other masks and/or from data on extra
help layers.
The basis for the creation of a mask layout is the schematic circuit description. Spice
netlists are systematic textual description of a circuit (arrow 1). Graphical editors
like Cadence-Composer or simple text editors are used to create spice netlists. A
spice circuit simulator checks the intended behavior of the schematic. At this
simulation stage, it is necessary to evaluate the behavior taking into account the
tolerances that exist on component values, on component models, on temperature...
Moreover, eventually before anything can start, a sound set of technical
specifications is the ultimate input to start up the whole design cycle. One last point
is missing: the design cycle is used both for sub-blocks of the chip circuit as for the
entire chip circuit. In other words, this cycle is repeated again and again, starting
with small sub-blocks and ending with the complete chip layout.
2.2 Lcos cell assembly technology highlights
This section describes design restrictions imposed by the cell assembly processes.
The first paragraph presents an lcos cell cross section along with the issues of spacer
technology and chip planarity. The second paragraph gives a quick look at the ways
reflective LC cells can be packaged and how electrical contact can be established.
The last paragraph collects a set of mask design rules intended to prevent design
errors that would jeopardize the yield of the panel assembly process.
2.2.1 The lcos cell structure
2.2.1.1 Cell cross section
Cell cross sections tell a lot about the structure of lcos panels. The cross sections
include cross sections of the silicon backplane; the text however must not disclose
3 not the ones from the haystack
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