MPC5642A - Freescale Semiconductor

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Introduction eMIOS 24 Channel 2 MB Flash Interrupt Controller 64-channel eDMA S0 3 KB Data RAM 14 KB Code RAM 128 KB SRAM eTPU2 32 Channel Power Architecture e200z4 SPE VLE MMU 8 KB I-cache Crossbar Switch MPU S2 S7 ADC – Analog to Digital Converter ADCi – ADC interface AMux – Analog Multiplexer BAM – Boot Assist Module CRC – Cyclic Redundancy Check unit DEC – Decimation Filter DTS – Development Trigger Semaphore DSPI – Deserial/Serial Peripheral Interface ECSM – Error Correction Status Module eDMA – Enhanced Direct Memory Access eMIOS – Enhanced Modular Input Output System eSCI – Enhanced Serial Communications Interface eTPU2 – Second gen. Enhanced Time Processing Unit FlexCAN – Controller Area Network FMPLL – Frequency-Modulated Phase-Locked Loop LEGEND JTAG – IEEE 1149.1 Test Controller MMU – Memory Management Unit MPU – Memory Protection Unit PMC – Power Management Controller PIT – Periodic Interrupt Timer RCOSC – Low-speed RC Oscillator REACM – Reaction Module SIU – System Integration Unit SPE – Signal Processing Extension SRAM – Static RAM STM – System Timer Module SWT – Software Watchdog Timer VGA – Variable Gain Amplifier VLE – Variable Length (instruction) Encoding XOSC – XTAL Oscillator Figure 1. MPC5642A series block diagram Table 2 summarizes the functions of the blocks present on the MPC5642A series microcontrollers. MPC5642A Microcontroller Data Sheet, Rev. 3.1 6 Freescale Semiconductor JTAG Nexus IEEE-ISTO 5001-2010 FlexRay M4 M0 M1 M6 REACM 6 ch DTS Analog PLL RCOSC XOSC I/O Bridge FMPLL CRC BAM PMC STM Debug S1 Voltage Regulator Standby Regulator with Switch PIT SWT SIU FlexCAN x 3 eSCI x 3 ECSM DSPI x 3 Temp Sens Calibration Bus Interface ADCi DEC x2 ADC ADC VGA AMux
Table 2. MPC5642A series block summary Block Function Boot assist module (BAM) Block of read-only memory containing executable code that searches for user-supplied boot code and, if none is found, executes the BAM boot code resident in device ROM Calibration bus interface Transfers data across the crossbar switch to/from peripherals attached to the calibration system connector Controller area network (FlexCAN) Supports the standard CAN communications protocol Crossbar switch (XBAR) Internal busmaster Cyclic redundancy check (CRC) CRC checksum generator Deserial serial peripheral interface (DSPI) Provides a synchronous serial interface for communication with external devices e200z4 core Executes programs and interrupt handlers Enhanced direct memory access (eDMA) Performs complex data movements with minimal intervention from the core. Enhanced modular input-output system (eMIOS) Enhanced queued analog-to-digital converter (eQADC) Enhanced serial communication interface (eSCI) Provides the functionality to generate or measure events Provides accurate and fast conversions for a wide range of applications Provides asynchronous serial communication capability with peripheral devices and other microcontroller units Enhanced time processor unit (eTPU2) Second-generation co-processor processes real-time input events, performs output waveform generation, and accesses shared data without host intervention Error Correction Status Module (ECSM) The Error Correction Status Module supports a number of miscellaneous control functions for the platform, and includes registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented Flash memory Provides storage for program code, constants, and variables FlexRay Provides high-speed distributed control for advanced automotive applications Frequency-modulated phase-locked loop (FMPLL) Generates high-speed system clocks and supports programmable frequency modulation Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests JTAG controller Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode Memory protection unit (MPU) Provides hardware access control for all memory references generated Nexus port controller (NPC) Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2010 standard Periodic interrupt timer (PIT) Produces periodic interrupts and triggers Reaction Module (REACM) Works in conjunction with the eQADC and eTPU2 to increase system performance by removing the CPU from the current control loop. MPC5642A Microcontroller Data Sheet, Rev. 3.1 Introduction Freescale Semiconductor 7
Page 1 and 2: Freescale Semiconductor Data Sheet:
Page 3 and 4: 1 Introduction 1.1 Document overvie
Page 5: CRC Yes FMPLL Yes VRC Yes Supplies
Page 9 and 10: 1.5 Feature details 1.5.1 e200z4 co
Page 11 and 12: 1.5.4 Interrupt controller (INTC) M
Page 13 and 14: — Glitch detection on reset input
Page 15 and 16: • 3 channels’ internal timebase
Page 17 and 18: 1.5.14 Enhanced queued analog-to-di
Page 19 and 20: 1.5.16 Enhanced serial communicatio
Page 21 and 22: MPC5642A Microcontroller Data Sheet
Page 23 and 24: 1.5.26 Nexus port controller (NPC)
Page 25 and 26: Freescale Semiconductor 25 MPC5642A
Page 49 and 50: 2.5 Signal details Table 4. Pad typ
Page 51 and 52: RCH0_[A:C] RCH1_[A:C] RCH2_[A:C] RC
Page 53 and 54: GPIO[12:17] GPIO[75:110] GPIO[113:1
Page 55 and 56: 3 Electrical characteristics MPC564
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MPC5642A Microcontroller Data Sheet
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Page 61 and 62:
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ID Name C Parameter Table 15. PMC e
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8 The 3.3V POR specs are also valid
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Table 19. Power sequence pin states
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I DD +I DDPLL CC P Operating curren
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R PUPD100K SR C Weak pull-up/down r
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3.9.1 I/O pad V RC33 current specif
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T SKEW CC D Differential skew Itphl
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3.11 Temperature sensor electrical
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Table 29. eQADC differential ended
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Table 33. Flash EEPROM module life
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Pad type C Medium 5,6,7 Slow 7,10 M
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Pad Data Input Pad Output Rising Ed
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NOTE The Nexus/JTAG Read/Write Acce
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TCK JCOMP 9 Figure 14. JTAG JCOMP t
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Table 38. Nexus debug port timing 1
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N TCK TMS, TDI TDO Package Nexus Wi
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3.17.4 Calibration bus interface ti
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CLKOUT OUTPUT BUS OUTPUT SIGNAL OUT
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3.17.5 External interrupt timing (I
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Table 46. DSPI timing 1,2 (continue
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PCSx SCK Output (CPOL = 0) SCK Outp
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PCSx SCK Output (CPOL = 0) SCK Outp
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3.17.9 eQADC SSI timing Table 47. e
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4 Packages 4.1 Package mechanical d
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Figure 36. 176 LQFP package mechani
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Figure 38. 208 MAPBGA package mecha
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Figure 40. 324 BGA package mechanic
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6 Document revision history Table 5
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