MPC5642A - Freescale Semiconductor

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Introduction Table 2. MPC5642A series block summary (continued) Block Function System Integration Unit (SIU) Controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. Static random-access memory (SRAM) Provides storage for program code, constants, and variables System timers Includes periodic interrupt timer with real-time interrupt; output compare timer and system watchdog timer System watchdog timer (SWT) Provides protection from runaway code Temperature sensor Provides the temperature of the device as an analog value MPC5642A Microcontroller Data Sheet, Rev. 3.1 8 Freescale Semiconductor
1.5 Feature details 1.5.1 e200z4 core MPC5642A Microcontroller Data Sheet, Rev. 3.1 Introduction MPC5642A devices have a high performance e200z4 core processor: • 32-bit Power Architecture technology programmer’s model • Variable Length Encoding (VLE) enhancements • Dual issue, 32-bit Power Architecture technology compliant CPU • 8 KB, 2/4-way set associative instruction cache • Thirty-two 64-bit general purpose registers (GPRs) • Memory Management Unit (MMU) with 24-entry fully-associative translation look-aside buffer (TLB) • Harvard Architecture: Separate instruction bus and load/store bus • Vectored interrupt support • Non-maskable interrupt input • Critical Interrupt input • New ‘Wait for Interrupt’ instruction, to be used with new low power modes • Reservation instructions for implementing read-modify-write accesses • Signal processing extension (SPE) APU • Single Precision Floating point (scalar and vector) • Nexus Class 3+ debug • Process ID manipulation for the MMU using an external tool • In-order execution and retirement • Precise exception handling • Branch processing unit — Dedicated branch address calculation adder — Branch target prefetching using 8-entry BTB • Supports independent instruction and data accesses to different memory subsystems, such as SRAM and flash memory via independent Instruction and Data BIUs • Load/store unit — 2-cycle load latency — Fully pipelined — Big and Little endian support — Misaligned access support • Signal Processing Extension (SPE1.1) APU supporting SIMD fixed-point operations using the 64-bit General Purpose Register file • Embedded Floating-Point (EFP2) APU supporting scalar and vector SIMD single-precision floating-point operations, using the 64-bit General Purpose Register file • Power management — Low power design – extensive clock gating — Power saving modes: wait — Dynamic power management of execution units, cache and MMU • Testability — Synthesizeable, MuxD scan design — ABIST/MBIST for arrays — Built-in Parallel Signature Unit Freescale Semiconductor 9
Page 1 and 2: Freescale Semiconductor Data Sheet:
Page 3 and 4: 1 Introduction 1.1 Document overvie
Page 5 and 6: CRC Yes FMPLL Yes VRC Yes Supplies
Page 7: Table 2. MPC5642A series block summ
Page 11 and 12: 1.5.4 Interrupt controller (INTC) M
Page 13 and 14: — Glitch detection on reset input
Page 15 and 16: • 3 channels’ internal timebase
Page 17 and 18: 1.5.14 Enhanced queued analog-to-di
Page 19 and 20: 1.5.16 Enhanced serial communicatio
Page 21 and 22: MPC5642A Microcontroller Data Sheet
Page 23 and 24: 1.5.26 Nexus port controller (NPC)
Page 25 and 26: Freescale Semiconductor 25 MPC5642A
Page 49 and 50: 2.5 Signal details Table 4. Pad typ
Page 51 and 52: RCH0_[A:C] RCH1_[A:C] RCH2_[A:C] RC
Page 53 and 54: GPIO[12:17] GPIO[75:110] GPIO[113:1
Page 55 and 56: 3 Electrical characteristics MPC564
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MPC5642A Microcontroller Data Sheet
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ID Name C Parameter Table 15. PMC e
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8 The 3.3V POR specs are also valid
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Table 19. Power sequence pin states
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I DD +I DDPLL CC P Operating curren
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R PUPD100K SR C Weak pull-up/down r
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3.9.1 I/O pad V RC33 current specif
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T SKEW CC D Differential skew Itphl
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3.11 Temperature sensor electrical
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Table 29. eQADC differential ended
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Table 33. Flash EEPROM module life
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Pad type C Medium 5,6,7 Slow 7,10 M
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Pad Data Input Pad Output Rising Ed
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NOTE The Nexus/JTAG Read/Write Acce
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TCK JCOMP 9 Figure 14. JTAG JCOMP t
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Table 38. Nexus debug port timing 1
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N TCK TMS, TDI TDO Package Nexus Wi
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3.17.4 Calibration bus interface ti
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CLKOUT OUTPUT BUS OUTPUT SIGNAL OUT
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3.17.5 External interrupt timing (I
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Table 46. DSPI timing 1,2 (continue
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PCSx SCK Output (CPOL = 0) SCK Outp
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PCSx SCK Output (CPOL = 0) SCK Outp
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3.17.9 eQADC SSI timing Table 47. e
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4 Packages 4.1 Package mechanical d
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Figure 36. 176 LQFP package mechani
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Figure 38. 208 MAPBGA package mecha
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Figure 40. 324 BGA package mechanic
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6 Document revision history Table 5
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