Power Management in Embedded Systems - DAIICT Intranet
Power Management in Embedded Systems - DAIICT Intranet
Power Management in Embedded Systems - DAIICT Intranet
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<strong>Power</strong> Dissapation <strong>in</strong> a CMOS<br />
● Two ma<strong>in</strong> sources of <strong>Power</strong> Dissapation <strong>in</strong> CMOS<br />
– Static/Leakage <strong>Power</strong> Dissapation: Results from leakage<br />
Current orig<strong>in</strong>at<strong>in</strong>g due to Resistive paths between Supply<br />
Voltage and Ground. Currently it contributes 15-20% of power<br />
dissapation at 130 nm technology. Exponentially <strong>in</strong>creases as<br />
chip technology moves ahead, below 100 nm<br />
– Dynamic/Switch<strong>in</strong>g <strong>Power</strong> Dissapation: results from<br />
switch<strong>in</strong>g capacitive loads between different Voltage levels i.e.<br />
dur<strong>in</strong>g clock transitions (largest component)<br />
– Short Circuit <strong>Power</strong> Dissapation: due to short circuit current<br />
when both transistors <strong>in</strong> a CMOS <strong>in</strong>verter are ON at the same<br />
time. Negligibly small, so we concentrate on first two sources<br />
of <strong>Power</strong> Dissapation
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