Power Management in Embedded Systems - DAIICT Intranet

More documents

Recommendations

Info

How to Reduce Power Consumption at CMOS (Hardware) Design Level ● Reduce Static Power Consumption by reducing supply voltage 'V' and choosing the system design accordingly ● Reduce Dynamic Power Dissapation by reducing Supply voltage 'V' ● Reduction of Operating Voltage: Voltage Scaling ● Reduction of Operating Frequency 'F': Frequency Scaling ● Reducing the switching coefficient of circuit 'A' ● Reducing the fraction of gates switching 'A' may not be possible, as its primary purpose may not be solved ● Reducing the circuit load capacity, 'C'
Reducing Standby Power Consumption ● Use separate power supply for combinational & sequential circuits [no power drawn by combinational circuit during standby] ● Reduce power supply to combinational circuit during standby ensuring that state is preserved ● Reducing V linearly reduces power
Page 1 and 2: Power Management in Embedded System
Page 3 and 4: Importance of Power Management ●
Page 5 and 6: Approaches to Power Management
Page 7 and 8: Static Power Management ● Deals w
Page 9 and 10: Recent Techniques: Hardware Level
Page 11: Power Dissapation in a CMOS ● Two
Page 15 and 16: Relationship between Energy & Frequ
Page 17 and 18: Dynamic Power Management ● Dynami
Page 19 and 20: PC's and embedded devices ● In PC
Page 21 and 22: Policy & Policy Managers ● DPM po
Page 23 and 24: Operating State ● If a system sup
Page 25 and 26: Congruence Class ● No device driv
Page 27 and 28: Task Example operating points opera
Page 29 and 30: Implementation ● assert_constrain
Page 31: References ● “Dynamic Power Man

Power Management in Embedded Systems - DAIICT Intranet

Create successful ePaper yourself

Delete template?

Save as template?