Tutorial #1 - MIT

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module datapath ( input [15:0] inst, // constant field from instruction input [31:0] rd1, // Reg[RA] from register file input [31:0] rd2, // Reg[RB] from register file (Reg[RC] for ST) input [31:0] pc_plus_4, // incremented PC input [31:0] branch_addr, // PC + 4 + 4*sxt(inst[15:0]) input [31:0] mem_rd_data, // memory read data (for LD) input asel, // select A operand for ALU input bsel, // select B operand for ALU input [1:0] wdsel, // select regfile write data input [5:0] alufn, // operation to be performed by alu output [31:0] wdata, // regfile write data (output of WDSEL mux) output [31:0] mem_addr, // alu output, doubles as data memory address output [31:0] jump_addr, // jump address (from Reg[RA]) output [31:0] mem_wr_data, // data memory write data (from Reg[RC]) output z // true if Reg[RA] is zero, used during branches ); wire [31:0] alu_a; // A input to ALU wire [31:0] alu_b; // B input to ALU // compute A and B inputs into alu, also Z bit for control logic dp_misc misc(asel,bsel,inst,rd1,rd2,branch_addr, alu_a,alu_b,jump_addr,mem_wr_data,z); // where all the heavy-lifting happens dp_alu alu(alufn,alu_a,alu_b,mem_addr); // Mux to select regfile write data from PC+4, alu output, and memory data dp_wdata_mux wdata_mux(wdsel,pc_plus_4,mem_addr,mem_rd_data,wdata); endmodule 6.884 – Spring 2005 02/09/05 T01 – Verilog 18
PC PCSEL 2 XAdr 4 ILL OP 3 JT 2 PC +4 1 0 00 Beta Control Signals PC+4+4*SXT(C) IRQ Z Instruction Memory Rc: 0 WA WA ASEL 1 0 6.884 – Spring 2005 02/09/05 + 1 A D Control Logic PCSEL RA2SEL ASEL BSEL WDSEL ALUFN Wr WERF WASEL Main Datapath XP Ra: 1 Z C: SXT() ALUFN 2 WASEL Rb: Register File RA1 RA2 RD1 RD2 JT A B ALU PC+4 0 1 2 Step 1: identify memories Step 2: identify datapaths What’s left is random logic … 1 0 1 0 WDSEL Rc: RA2SEL WD WE BSEL WD Data Memory Adr 1 WERF RD R/W 1 Wr T01 – Verilog 19
Page 1 and 2: % vcs mips.v % ./simv % vcs -RPP &
Page 3 and 4: Tour of the 6.884 Athena Locker To
Page 5 and 6: A_in B_in Greatest Common Divisor C
Page 7 and 8: A_in B_in GCD Test Harness 6.884 -
Page 9 and 10: Building a GCD Simulator with VCS %
Page 11 and 12: Viewing Waveforms with VirSim 6.884
Page 13 and 14: Using the mkasic.pl Script gcd/ mka
Page 15 and 16: PC PCSEL 2 XAdr 4 ILL OP 3 Beta Mic
Page 17: module regfile ( input [4:0] ra1, /
Page 21 and 22: module control( ... ); // Control R
Page 23 and 24: Building Beta + Running Programs %
Page 25 and 26: Lab1 Pipelined Datapath 6.884 - Spr
Page 27 and 28: `include "mips_cpu.v" Lab1 Test Har
Page 29 and 30: Building Tests with smips-testbuild

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