Tutorial #1 - MIT

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iaddr instr addr wen write_data read_data Lab1 Test Harness mips_cpu 6.884 – Spring 2005 02/09/05 clk reset interrupt tohost fromhost T01 – Verilog 26
`include "mips_cpu.v" Lab1 Test Harness module mips_tester; reg clk = 0; // Clock to core. reg reset = 0; // Reset signal. reg int_ext = 0; // Interrupt signal. reg [7:0] fromhost = 8'b0; // Control reg to CPU. wire [7:0] tohost; // Control reg from CPU. wire [31:0] addr; // Data address. wire wen; // Write enable. wire [31:0] read_data; // Read data back to CPU. wire [31:0] write_data; // Write data from CPU. wire [31:0] iaddr; // Fetch address. wire [31:0] inst; // Instruction. always #5 clk = ~clk; // Clock generator (10ns clock period) reg [ 1023:0 ] exe_filename; mips_cpu mips(clk, reset, int_ext, fromhost, tohost, addr, wen, write_data, read_data, iaddr, inst); memory mem(clk, addr, wen, write_data, read_data, iaddr, inst); ... 6.884 – Spring 2005 02/09/05 T01 – Verilog 27
Page 1 and 2: % vcs mips.v % ./simv % vcs -RPP &
Page 3 and 4: Tour of the 6.884 Athena Locker To
Page 5 and 6: A_in B_in Greatest Common Divisor C
Page 7 and 8: A_in B_in GCD Test Harness 6.884 -
Page 9 and 10: Building a GCD Simulator with VCS %
Page 11 and 12: Viewing Waveforms with VirSim 6.884
Page 13 and 14: Using the mkasic.pl Script gcd/ mka
Page 15 and 16: PC PCSEL 2 XAdr 4 ILL OP 3 Beta Mic
Page 17 and 18: module regfile ( input [4:0] ra1, /
Page 19 and 20: PC PCSEL 2 XAdr 4 ILL OP 3 JT 2 PC
Page 21 and 22: module control( ... ); // Control R
Page 23 and 24: Building Beta + Running Programs %
Page 25: Lab1 Pipelined Datapath 6.884 - Spr
Page 29 and 30: Building Tests with smips-testbuild

Tutorial #1 - MIT

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