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A_in<br />
B_in<br />
Greatest Common Divisor<br />
Control Unit<br />
go A A<br />
mux reg<br />
B<br />
mux<br />
B<br />
reg<br />
out<br />
mux<br />
done<br />
sel en sel en B = 0<br />
A < B<br />
sel<br />
6.884 – Spring 2005 02/09/05<br />
A<br />
B<br />
zero? lt<br />
sub<br />
out<br />
T01 – Verilog 5
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