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POWER CONTROLloops dB ° 40.0 20.0 0 –20.0 –40.0 180 |T (f)| 90.0 0 –90.0 –180 T (f) –2 dB –10 dB φ m 45° φ φm 0° m 0° Where corresponds to the frequency point where is exactly -180° or radians (1 MHz in Fig. 3). Fig. 4. portrays typical gain variations of ±10 dB due to production spreads in the selected components. It brings the crossover frequency from 1.5 kHz to 30 kHz. In this area, the phase margin changes from 70° to 45°, safe numbers according to theory. What is the worst case? It is when the new crossover frequency occurs where the total phase lag is 180°, matching the conditions for oscillations. This condition occurs at 1 MHz, implying a positive gain change of 35 dB. LARGE GAINS UNLIKELY Fortunately, deviations of 35 dB are unlikely to happen in modern electronics circuits. Time ago, when amplifiers or servomechanisms were driven by vacuum tubes-based circuits, warm-up times during the poweron sequence could induce large loop gain variations. Gain provisions were thus necessary to reject a second point where the stability could be in danger. This gain margin, identified on the loop gain curve at the frequency where the total phase lag reaches -180°, is noted GM in Fig. 3. In modern electronic circuits, gain margins beyond 10 dB are usually enough, unless your loop gain exhibits extreme sensitivity to an external parameter. Another example of gain shift appears in Fig. 5. It shows another compensated converter exhibiting a phase margin of 80° at 10 kHz. Based on what we discussed, we know that gain changes can occur, inducing ups or downs on the gain curve. In our example, we can identify an area around 2 kHz where the phase margin is as Crossover frequency f c = 10 6.5 kHz c φ = 50° m 10 100 1k Frequency (Hz) 10k 100k Fig. 6. The phase lags beyond 180° but in an area where the gain is larger than 1. This is not a problem, and the response is acceptable. small as 18°. If a gain decrease of 20-25 dB occurs, you can end up with a control system showing a dangerously low phase margin around 2 kHz. It would lead to an oscillatory response, perhaps exceeding the overshoot specifications. This kind of system is told to be conditionally stable. Fortunately, as already said, a 25-dB variation of gain is unusual and such a system can be considered robust with this gain margin. However, I have seen design cases where the end user (your customer) clearly stated in the specifications that conditional designs were not acceptable, asking for a phase margin greater than 60° at all points below the crossover frequency. In this case, it becomes mandatory to compensate the converter so that no region of reduced phase margins below crossover ever exist whatever the operating conditions are. STABLE OR UNSTABLE? It is often believed that a system where the phase dips below -180° before crossover is an unstable system. Such a response appears in Fig. 6. The phase curve quickly drops after 1 kHz and passes the -180° limit at 1.5 kHz for a few kilohertz. It then goes up again to offer a phase margin of 50° at 10 kHz. Yes, this system is stable simply because we do not satisfy (3.7) at 0 dB. Remember, to cancel the denominator of (3.3), you must have the gain magnitude exactly equal to 1 and a phase lag of 180° or beyond. In the graph, we can see that this condition is not satisfied at any point in the picture. However, it is worth noting that the loop is highly conditional. Should the gain reduce by a few decibels and your phase margin becomes less than 45°. Another 10-dB decrease and you enter a dangerous area of zero phase margin where, this time, the oscillation criteria would be met. Note: This article is reprinted from the book “Designing Control Loops for Linear and Switching Power Supplies: A Tutorial Guide,” (c) 2012, with permission of the publisher, Artech House, Inc., Boston. The subjects in the book include: Basics of Loop Control, Transfer Functions, Stability Criteria of a Control System, Compensation, Operational Amplifier-Based Compensation, Operational Transconductance Amplifier-Based Compensation, TL-431-Based Compensation, Shunt Regulator-Based Compensation, Measurements and Design Examples. The book can be purchased at ArtechHouse.com, Amazon.com, or BN.com 18 Power Electronics Technology | June 2013 www.powerelectronics.com
DESIGNfeature MICHAEL DE ROOIJ, Ph.D., Executive Director of Applications Engineering, Efficient Power Conversion Corporation JOHAN STRYDOM, Ph.D., Vice President, Applications, Efficient Power Conversion Corporation eGaN ® FET- Silicon Power Shoot- Out: Small Signal RF Performance In this eGaN FET-silicon power shoot-out series article, we examine RF performance using the 200 V EPC2012 [3] eGaN FET as a starting point. The eGaN FET is optimized as a power-switching device but also exhibits good RF characteristics. Future eGaN FET parts can be optimized for better RF performance at higher frequencies. 1621 Gate Circuit Reference Plane Device Outline 914 349 271 135.3 Unlike power switching FETs, RF FETs are designed to work best in the linear region of operation to maximize power gain and minimize distortion, whereas power switching devices are optimized for lowest R DS(ON) and gate charge [1,2,3,17,18,19,20]. Another significant difference between power switching and RF FETs is the power dissipation capability of RF devices is significantly higher than that of power switching devices for equivalent terminal characteristics to accommodate the higher power losses in the linear region. We will focus on RF characterization in the frequency range from 200 MHz through 2.5 GHz, the results of which can be used to design a pulsed power RF amplifer. RF CHARACTERIZATION Prior to being able to compare various RF FETs with each other they need to be properly characterized, which can accomplished by measuring the S-parameters of the FET while regarding it as a 2-port network under controlled bias conditions. A test fixture was designed for the EPC2012 to connect the RF signals to the FET and to provide the necessary S-parameter measurement reference planes from which the dataset would be valid. The test fixture design used a 30 mil thick Rogers 4350 substrate [21] , chosen for its low losses at higher frequencies. This allowed the design to be suitable for frequencies as high as 12 GHz. Fig. 1 shows the reference plane design and highlights the outline of the EPC2012 device. The transmission lines to the device Gate and Drain were designed as microstrip transmission lines with 50 Ω characteristic impedance. 271 914 1621 Drain Circuit Reference Plane Fig. 1. Reference plane design for the EPC2012 eGaN FET using a 30 mil thick Rogers 4350 substrate. The test fixture was also equipped with a negative temperature co-efficient thermistor (NTC) placed in close proximity to the source pad of the eGaN FET to provide an indication of the temperature of the copper in that area without affecting the RF performance. The EPC9903 test fixture in Fig. 2 shows the right side image showing the top mounted heat-sink. The EPC FET has a lower thermal resistance [3] from junction to the top side of the device, compared to the bottom side (soldered), and hence mounting the heat-sink to the back side of the device has a high impact on the power dissipation capability of the device. Due to thermal limitations of the test fixture and the EPC2012 device, testing of the eGaN FET was pulsed with a low duty cycle with the average power dissipation kept below 0.7 W without the heat-sink, and 5 W with the heat-sink and forced air cooling. The heat-sink used was 15 mm x 15 mm x 14.5 mm high, supplied by www.powerelectronics.com June 2013 | Power Electronics Technology 19
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