The Stack, Subroutines, Interrupts, and Resets: Ch3 Spasov

The Stack, Subroutines, 

Interrupts, and Resets: 

Ch3 Spasov 

A. The stack 

B. Subroutines 

C. Interrupts 

D. Resets 

The 

STACK 

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 1 

The stack is a special area in memory used by the CPU to store 

register information or general data information during program 

execution 

The stack has a top and a bottom 

The SP register is the special register that controls the address 

in the stack 

The stack used is a LIFO structure that uses push and pull 

(pop) operations 

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 2

Using the 

STACK 

push operations: 

PSHA, PSHB, PSHX, and PSHY 

pull operations 

PULA, PULB, PULX, and PULY 

Sometimes we push the register data onto the stack when we 

need to load the registers with other values to perform certain 

operations ... 


Stack as a Storage Buffer 

* Listing 3.1 

* SUM OF SQUARES 

* Demonstrate push and pull operations 

* Program calculates x squared plus y squared. 

* It gets x and y as 8-bit numbers from addresses 

* $1031 and $1032. 

* It puts the 8-bit result in ACCA. 

ORG $E000 ;start address of program 

BEGIN LDS #$FF ;You must define the stack first 

LDAA $1031 ;Get first data, x 

TAB ;and square it 

MUL 

ADCA #$00 ;round it to 8-bit result 

PSHA ;and save it 

LDAA $1032 ;Get second data, y 

TAB 

MUL 

;and square it 


PULB ;retrieve first result 

ABA ;and add them 

HERE BRA HERE ;For now, stop program 


Using Subroutines 

A subroutine allows us to reuse code. It is a section of 

a program that may be used one or more times 

The main program calls subroutines to perform 

certain steps 

A data input/output process for subroutines is called 

parameter passing 

If there are not enough registers for parameter passing, a 

calling program can pass more parameters using stack 

Ex: Modify the program from the previous slide to add 

many squares 

Subroutine Example 


* SUM OF SQUARES: Demonstrate subroutines 

* Program squares all the numbers in addresses $C000 to $C07F 

* and puts the sum of the squares as a 16-bit result in IX. 

ORG $E000 ;start address 

* Start MAIN 

MAIN LDS #$CFFF ;You must define 

* ;the stack first squaring loop 

LDX #$C000 ;init. data block pointer 

LOOP1 

JSR SQUARE ;square it and point to next data 

PSHA ;save square 

CPX #$C080 ;squared all data? 

BNE LOOP1 ;get more if not 

* ;summing loop 

LDX #$0000 ;sum = 0 

LDAA #$80 ;i=$80 

LOOP2 PULB ;get square(i) 

ABX ;sum = sum + square(i) 

DECA ;i=i-1 

BNE LOOP2 ;repeat until i == 0 

HERE BRA HERE ;stop program 

* End of MAIN 

* ---------------------------------------------------- 


Subroutine Example 

* SUBROUTINE SQUARE 

* calculates the square of an 8-bit number 

* as a rounded 8-bit normalized result 

* data pointer (IX) increments 

* calling registers: 

* IX = address of data to be squared 

* return registers: 

* ACCA = 8-bit square 

* IX=IX+1 

* ACCB is affected 

* others unaffected 

SQUARE 

LDAA $0,X 

TAB 

MUL 


INX 

RTS 


* ----------------------------------------------------- 

Process of Calling Subroutines 


Example: Subroutine Using the Stack 

* Listing 3.6 

* Demonstrate a convention for using subroutines 

* using a modification of Subroutine SQUARE 

* (See Listing 3.2). Program squares all the numbers 

* in addresses $C000 to $C07F 

ORG $E000 ;start address 

* Start MAIN 

MAIN LDS #$FF ;You must define the stack first 

* ;squaring loop 

LDX #$C000 ;init. data block pointer 

* ;IX is the calling register 

LOOP1 

JSR SQUARE2 ;square it and note that 

* ;original IX value returned 

INX ;point to next data 

CPX #$C080 ;squared all data? 

BNE LOOP1 ;get more if not 

HERE 

* End of MAIN 

BRA HERE ;stop program 



* SUBROUTINE SQUARE2 

* calculates the square of an 8-bit number as a rounded 8-bit result 

* data pointer (IX) increments 

* calling registers:IX = address of data to be squared 

* return registers: IX = address of 8-bit square 

* CCR affected; others unaffected 

SQUARE2 

PSHA ;preserve registers 

PSHB 

* ;note that following instructions modify 

* ;ACCA and ACCB 

LDAA $0,X ;get data to square 

TAB ;copy it to ACCB 

MUL ;square it 


STAA $0,X ;store result 

PULB ;restore registers 

PULA 

RTS ;return, note that ACCA and ACCB 

* ;contain their original values 



The number of pushes must be equal with the number of pulls 






Typical Program Execution 

Without interrupts the program executes continuously 


Resets 

A reset is a special type of interrupt 

Unlike an interrupt, it does not return to the interrupted 

program 

A reset stops execution of the application program to do a 

special function, such as reinitializing the registers and 

memory 

Resets 

and 

Interrupts 



The 68HC11 has four possible types of 

reset 

External RESET^ pin 

Power-on reset (POR) 

Computer operating 

properly (COP) 

Clock monitor reset 

Types 1 and 2 are external resets 

and types 3 and 4 are fault 

tolerant resets or internal resets. 

Other differences between resets and interrupts are: 

•Reset exception is immediately recognized asynchronously 

to the clock 

•MCU stays in the reset state as long as reset signal is active 

•An interrupt is only sampled by the CPU at the end of instr. seq. 

Interrupt 

External 

RESET 

Q: How does MCU knows 

the source of RESET? 


An interrupt suspends the execution of an application to 

do something else – it is triggered by an interrupt request 

An interrupt service routine (ISR) is initiated 

RTI instruction has to be at the end of the ISR to load registers 


Interrupt Vector 

All resets and interrupts 

use vectors 

A vector indicates the 

start address of reset or 

interrupt routines 

A vector address is a 2byte 

memory location 

that stores a vector 

Typical Motorola 

processors use a single 

area of memory to store 

the vectors => known as 

the vector table 

We can divide the 

interrupt sources into 

four groups: 

interrupts from on-chip 

resources 

external interrupts 

software interrupts 

and reset exceptions 



CPU Interrupt 

Processing 

The interrupt process 

consists of hardware that 

detects an event and signals 

the CPU 

The CPU changes the 

program flow to the Interrupt 

Service Routine 

The process in the side 

diagram is called exception 

processing because the CPU 

will execute the next 

instruction except when one 

of the interrupts is pending 

An interrupt is said to be 

pending when it is enabled, 

its event has been detected, 

and it has not been serviced 


Pending Interrupt Detection 

Most interrupts are detected by the on-chip resource 

Only IRQ and XIRQ are detected directly by the CPU 

The CPU checks the interrupt signals from all sources 

after it had finished executing each instruction 

The interrupt signals from on-chip resources are 

implemented either as event flags that must be 

cleared explicitly or as automatic event flags 

IRQ and XIRQ are active-low signals, so these 

sources are serviced as long as the interrupt signal is 

low 


Saving Context 

Once a pending interrupt is 

detected, CPU11, 12 saves 

the context by pushing all the 

CPU registers onto the stack 

All registers must be saved 

because the interrupt is 

asynchronous to the 

program flow and we cannot 

predict when it will occur 

At the end of ISR the RTI 

instruction restores the 

context of the interrupted 

program 

Set Interrupt Masks 


After context save, CPU sets the appropriate 

masks 

if the interrupt source is one controlled by the I 

mask, then I will be set automatically 

if the interrupt source is the XIRQ, then both X and 

I masks are set 

This is done to prevent nested interrupts 

before the system is ready 


Vectors 

Next step is to get the interrupt service routine 

An interrupt vector is two fixed memory locations that 

contain the address of the ISR for a given interrupt 

The CPU 11 interrupt vectors are stored at addresses 

shown in slide 22 

So, for example, to load the interrupt vector for a 

service routine you could do: 

ORG $vector 

FDB ISRname ; form double byte 


Multiple Interrupts and Priority 

When a system has more 

than one interrupt source 

enabled, it must be able to 

handle the condition when 

more than one interrupt is 

pending at the same time 

Since the CPU can only 

handle a single interrupt at a 

time, a priority is assigned to 

each source 

The CPU then services the 

highest priority pending 

interrupt first 

If the ISR does not reset the 

I bit, only nonmaskable 

interrupts or resets can 

interrupt this service routine 

The ISR could clear I bit to 

allow itself to be interrupted 

Execution of the RTI restores 

the original condition of the I 

bit then the lower-priority 

interrupt can be serviced 


Software Interrupts 

A software interrupt is an 

instruction that initiates the 

interrupt process 

In the CPU11 and CPU12 

the software interrupt 

instruction is SWI 

Software interrupts should 

be used exclusively for 

debugging tools such as 

software breakpoints in 

debug monitors and 

emulators 

SWI is a single byte opcode 

instruction 

When a breakpoint is 

reached in a debug monitor 

the monitor program 

substitutes the instruction at 

that address with an SWI 

When the monitor is finished 

the SWI opcode is replaced 

with the original opcode 

Another use for SWI is as a 

subroutine that preserves the 

registers automatically 



Software Interrupts 

Another instructions that are used in the 

interrupt process are WRI and STOP 

These instructions are useful when the 

program can be in a wait mode while waiting 

for an interrupt 

in the wait mode the 68HC11 can reduce its power 

consumption 





* PIOC configured as shown in Figure 9.13 

* and all other required initialization has been done. 

ORG $100 

LDY #PTR ;initialize data pointer 

CLI ;enable interrupts 

REPEAT 

WAI ;wait for falling STRA 

* ;to cause interrupt 

LDAA 0,Y ;send out data when it occurs 

STAA PORTB,X 

* ;note, MCU also pulses STRB low for 2 E-cycles 

INY ;repeat for next data transfer 

BRA REPEAT 

RIRQ 

* This is the interrupt handler routine for parallel I/O 

* Note it has the same vector ($FFF2,F3) as IRQ 

LDAA PIOC,X ;these two instructions clear STAF 

LDAA PORTCL,X 

RTI 

PTR EQU $180 



STOP 

Instruction 



Standard 

Definitions 

External Interrupts 

There are 2 external interrupt 

pins on the CPU11 and 12 

IRQ – is an active-low, 

maskable interrupt signal 

request 

XIRQ – is an active-low, 

pseudo-nonmaskable 

interrupt request 

By default, when you power 

up the MPU or RESET it, 

XIRQ is masked, that is: 

The X bit in CCR is set 


To unmask XIRQ, you use 

the TAP instruction to clear 

bit X 

Once the program has 

cleared it, executing another 

TAP will not set X again 

The only way to set X is to 

RESET the 68HX11 

TPA ;CCR -> A 

ANDA #$BF; reset bit 6 (X) 

TAP ;A -> CCR 


68HC11 

Interrupts 



Changing Priority 

HPRIO – highest priority 

interrupt register 

may be read at any time 

but may only be written 

under special 

circumstances 

interrupts obey a fixed 

hardware-priority circuit to 

resolve simultaneous 

requests 

However, an I-bit-related 

interrupt source may be 

elevated to the highest I-bit 

priority position in the 

resolution circuit 

The first six interrupts are not 

masked by the I bit in the 

CCR and have a fixed 

priority: 

reset, clock monitor fail, 

COP fail, illegal opcode 

and XIRQ 

HPRIO may only be written 

while the I-bit related 

interrupts are inhibited (I=1) 



External 

Interrupt 

Design 

Approach 





How to 

Establish 

the 

Vector 



IRQ Interrupt Request 

Interrupt 

Polling 

Using 

Linked 

Lists 



6811 Assembly Structure for Interrupt 

Polling using Linked Lists 



Periodic 

Polling 

Plus 

Real 

Time Interrupts 



6811 Registers 

Used to 

Configure the 

RTI 



68HC11 Assembly Language Implementation of a Periodic Interrupt 

Using RTI

The Stack, Subroutines, Interrupts, and Resets: Ch3 Spasov

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