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1.1.3 Program Counter MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL Introduction The PC contains the address of the instruction currently executing. During instruction execution and exception processing, the processor automatically increments the contents or places a new value in the PC. For some addressing modes, the PC can be used as a pointer for PC relative addressing. 1.1.4 Condition Code Register Consisting of five bits, the CCR, the status register’s lower byte, is the only portion of the status register (SR) available in the user mode. Many integer instructions affect the CCR, indicating the instruction’s result. Program and system control instructions also use certain combinations of these bits to control program and system flow. The condition codes meet two criteria: consistency across instructions, uses, and instances and meaningful results with no change unless it provides useful information. Consistency across instructions means that all instructions that are special cases of more general instructions affect the condition codes in the same way. Consistency across uses means that conditional instructions test the condition codes similarly and provide the same results whether a compare, test, or move instruction sets the condition codes. Consistency across instances means that all instances of an instruction affect the condition codes in the same way. The first four bits represent a condition of the result generated by an operation. The fifth bit or the extend bit (X-bit) is an operand for multiprecision computations. The carry bit (C-bit) and the X-bit are separate in the M68000 family to simplify programming techniques that use them (refer to Table 3-18 as an example). In the instruction set definitions, the CCR is illustrated as follows: X N Z V C X—Extend Set to the value of the C-bit for arithmetic operations; otherwise not affected or set to a specified result. N—Negative Set if the most significant bit of the result is set; otherwise clear. Z—Zero Set if the result equals zero; otherwise clear. V—Overflow Set if an arithmetic overflow occurs implying that the result cannot be represented in the operand size; otherwise clear. 1-3
Introduction C—Carry Set if a carry out of the most significant bit of the operand occurs for an addition, or if a borrow occurs in a subtraction; otherwise clear. 1.2 FLOATING-POINT UNIT USER PROGRAMMING MODEL The following paragraphs describe the registers for the floating- point unit user programming model. Figure 1-2 illustrates the M68000 family user programming model’s floating-point portion for the MC68040 and the MC68881/MC68882 floating-point coprocessors. It contains the following registers: 1-4 • 8 Floating-Point Data Registers (FP7 – FP0) • 16-Bit Floating-Point Control Register (FPCR) • 32-Bit Floating-Point Status Register (FPSR) • 32-Bit Floating-Point Instruction Address Register (FPIAR) 79 63 0 31 31 23 CONDITION CODE Figure 1-2. M68000 Family Floating-Point Unit User Programming Model 1.2.1 Floating-Point Data Registers (FP7 – FP0) 0 QUOTIENT These floating-point data registers are analogous to the integer data registers for the M68000 family. They always contain extended- precision numbers. All external operands, despite the data format, are converted to extended-precision values before being used in any calculation or being stored in a floating-point data register. A reset or a null-restore operation sets FP7 – FP0 positive, nonsignaling not-a-numbers (NANs). M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 15 15 EXCEPTION ENABLE EXCEPTION STATUS 7 7 MODE CONTROL ACCRUED EXCEPTION 0 0 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FPCR FPSR FPIAR FLOATING-POINT DATA REGISTERS FLOATING-POINT CONTROL REGISTER FLOATING-POINT STATUS REGISTER FLOATING-POINT INSTRUCTION ADDRESS REGISTER MOTOROLA
Page 2 and 3: © MOTOROLA INC., 1992 MOTOROLA M68
Page 4 and 5: Paragraph Number iv TABLE OF CONTEN
Page 6 and 7: Paragraph Number vi TABLE OF CONTEN
Page 8 and 9: Figure Number MOTOROLA LIST OF FIGU
Page 10 and 11: Table Number MOTOROLA LIST OF TABLE
Page 12 and 13: SECTION 1 INTRODUCTION This manual
Page 16 and 17: 1.2.2 Floating-Point Control Regist
Page 18 and 19: MOTOROLA M68000 FAMILY PROGRAMMER
Page 20 and 21: Registers MOTOROLA 68000 68008 68HC
Page 24 and 25: E—Enable 0 = Transparent translat
Page 26 and 27: 1.5 FLOATING-POINT DATA FORMATS MOT
Page 30 and 31: 1.6.3 Zeros Introduction Zeros can
Page 32 and 33: Table 1-4. Single-Precision Real Fo
Page 34 and 35: Table 1-6. Extended-Precision Real
Page 36 and 37: 1.7 ORGANIZATION OF DATA IN REGISTE
Page 38 and 39: Introduction Control registers vary
Page 40 and 41: BYTE n - 1 7 0 7 0 7 0 BYTE n - 1 A
Page 42 and 43: SECTION 2 ADDRESSING CAPABILITIES M
Page 44 and 45: MOTOROLA Table 2-1. Instruction Wor
Page 46 and 47: 2.2.1 Data Register Direct Mode MOT
Page 48 and 49: 2.2.5 Address Register Indirect wit
Page 52 and 53: 2.2.9 Memory Indirect Postindexed M
Page 54 and 55: 2.2.11 Program Counter Indirect wit
Page 58 and 59: 2.2.15 Program Counter Memory Indir
Page 60 and 61: 2.2.18 Immediate Data MOTOROLA M680
Page 62 and 63: 2.4 BRIEF EXTENSION WORD FORMAT COM
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A6 = 0 1 2 3 A6 = 0 A6 = 0 1 SIMPLE
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2.5.2 Memory Indirect Modes Address
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. Addressing Capabilities 2.5.2.3 M
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Addressing Capabilities To implemen
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SECTION 3 INSTRUCTION SET SUMMARY T
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MOTOROLA Table 3-1. Notational Conv
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3.1.1 Data Movement Instructions MO
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MOTOROLA M68000 FAMILY PROGRAMMER
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Table 3-5. Shift and Rotate Operati
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3.1.7 Binary-Coded Decimal Instruct
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Table 3-10. System Control Operatio
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3.1.12 Memory Management Unit (MMU)
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Table 3-17. Monadic Floating-Point
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LSR (r = 0) — * * 0 0 ROXL (r = 0
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Instruction Set Summary extends the
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3.5 FLOATING-POINT COMPUTATIONAL AC
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3.5.2 Rounding the Result Instructi
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Instruction Set Summary intermediat
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Table 3-22. FPCC Encodings Data Typ
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Table 3-23. Floating-Point Conditio
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INSTRUCTION NAME APPLICABLE PROCESS
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Integer Instructions ABCD Operation
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Integer Instructions ADD Operation:
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Integer Instructions ADD 4-6 Add (M
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Integer Instructions ADDA 4-8 Add A
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Integer Instructions ADDI Add Immed
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Integer Instructions ADDQ Add Quick
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Integer Instructions ADDX Add Exten
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Integer Instructions AND AND Logica
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Integer Instructions ANDI AND Immed
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Integer Instructions ANDI ANDI to C
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Integer Instructions ASL, ASR Arith
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Integer Instructions ASL, ASR Arith
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Integer Instructions Bcc Branch Con
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Integer Instructions BCHG Test a Bi
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Integer Instructions BCLR Test a Bi
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Integer Instructions BCLR Test a Bi
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Integer Instructions BFCHG Test Bit
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Integer Instructions BFCLR Test Bit
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Integer Instructions BFEXTS Extract
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Integer Instructions BFEXTU Extract
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Integer Instructions BFEXTU Extract
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Integer Instructions BFFFO Find Fir
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Integer Instructions BFINS Insert B
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Integer Instructions BFINS Insert B
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Integer Instructions BFSET Test Bit
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Integer Instructions BFTST Test Bit
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Integer Instructions BKPT Breakpoin
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Integer Instructions BSET Test a Bi
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Integer Instructions BSET Test a Bi
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Integer Instructions BSR Branch to
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Integer Instructions BTST Test a Bi
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Integer Instructions CALLM Call Mod
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Integer Instructions CAS CAS CAS2 C
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Integer Instructions CAS CAS CAS2 C
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Integer Instructions CHK Check Regi
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Integer Instructions CHK2 Check Reg
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Integer Instructions CLR Clear an O
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Integer Instructions CMP Compare CM
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Integer Instructions CMPA Compare A
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Integer Instructions CMPI Compare I
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Integer Instructions CMP2 Compare R
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Integer Instructions cpBcc Branch o
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Integer Instructions cpGEN Coproces
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Integer Instructions cpScc Set on C
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Integer Instructions DBcc Test Cond
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Integer Instructions DIVS, DIVSL Si
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Integer Instructions DIVS, DIVSL Si
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Integer Instructions DIVU, DIVUL Un
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Integer Instructions DIVU, DIVUL Un
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Integer Instructions EOR Exclusive-
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Integer Instructions EORI Exclusive
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Integer Instructions EORI EORI to C
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Integer Instructions EXT, EXTB Sign
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Integer Instructions JMP Jump JMP (
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Integer Instructions LEA Load Effec
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Integer Instructions LINK Link and
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Integer Instructions LSL, LSR Logic
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Integer Instructions MOVE Move Data
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Integer Instructions MOVE Move Data
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Integer Instructions MOVEA Move Add
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Integer Instructions MOVE MOVE from
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Integer Instructions MOVE MOVE to C
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Integer Instructions MOVE16 Move 16
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Integer Instructions MOVEM Move Mul
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Integer Instructions MOVEM Move Mul
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Integer Instructions MOVEP Move Per
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Integer Instructions MOVEQ Move Qui
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Integer Instructions MULS Signed Mu
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Integer Instructions MULU Unsigned
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Integer Instructions MULU Unsigned
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Integer Instructions NBCD Negate De
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Integer Instructions NEG Negate NEG
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Integer Instructions NEGX Negate wi
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Integer Instructions NOT Logical Co
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Integer Instructions OR Inclusive-O
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Integer Instructions OR Inclusive-O
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Integer Instructions ORI Inclusive-
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Integer Instructions PACK Pack PACK
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Integer Instructions PACK Pack PACK
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Integer Instructions ROL, ROR Rotat
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Integer Instructions ROL, ROR Rotat
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Integer Instructions ROXL, ROXR Rot
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Integer Instructions RTD Return and
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Integer Instructions RTR Return and
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Integer Instructions SBCD Subtract
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Integer Instructions Scc Set Accord
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Integer Instructions SUB Subtract S
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Integer Instructions SUB Subtract S
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Integer Instructions SUBA Subtract
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Integer Instructions SUBI Subtract
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Integer Instructions SUBQ Subtract
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Integer Instructions SUBX Subtract
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Integer Instructions TAS Test and S
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Integer Instructions TRAP Trap TRAP
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Integer Instructions TRAPcc Trap on
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Integer Instructions TST Test an Op
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Integer Instructions UNLK Unlink UN
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Integer Instructions UNPK Unpack BC
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Integer Instructions 4-198 M68000 F
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Floating Point Instructions 5-2 Tab
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Floating Point Instructions FABS Op
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Floating Point Instructions FABS In
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Floating Point Instructions FACOS O
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Floating Point Instructions FACOS 5
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Floating Point Instructions FADD Fl
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Floating Point Instructions FASIN A
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Floating Point Instructions FASIN A
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Floating Point Instructions FATAN A
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Floating Point Instructions FATANH
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Floating Point Instructions FATANH
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Floating Point Instructions FBcc Fl
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Floating Point Instructions FCMP Fl
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Floating Point Instructions FCOS Co
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Floating Point Instructions FCOS Co
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Floating Point Instructions FCOSH H
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Floating Point Instructions FDBcc F
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Floating Point Instructions FDIV Fl
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Floating Point Instructions FDIV Fl
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Floating Point Instructions FETOX e
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Floating Point Instructions FETOX e
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Floating Point Instructions FETOXM1
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Floating Point Instructions FGETEXP
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Floating Point Instructions FGETEXP
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Floating Point Instructions FGETMAN
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Floating Point Instructions FINT In
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Floating Point Instructions FINT In
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Floating Point Instructions FINTRZ
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Floating Point Instructions FLOG10
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Floating Point Instructions FLOG10
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Floating Point Instructions FLOG2 L
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Floating Point Instructions FLOGN L
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Floating Point Instructions FLOGN L
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Floating Point Instructions FLOGNP1
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Floating Point Instructions FMOD Mo
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Floating Point Instructions FMOD Mo
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Floating Point Instructions FMOVE M
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Floating Point Instructions FMOVECR
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Floating Point Instructions FMOVEM
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Floating Point Instructions FMUL Fl
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Floating Point Instructions FMUL Fl
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Floating Point Instructions FNEG Fl
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Floating Point Instructions FNEG Fl
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Floating Point Instructions FNOP No
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Floating Point Instructions FREM IE
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Floating Point Instructions FREM IE
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Floating Point Instructions FSCALE
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Floating Point Instructions FScc Se
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Floating Point Instructions FSGLDIV
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Floating Point Instructions FSGLDIV
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Floating Point Instructions FSGLMUL
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Floating Point Instructions FSIN Si
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Floating Point Instructions FSIN Si
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Floating Point Instructions FSINCOS
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Floating Point Instructions FSINCOS
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Floating Point Instructions FSINH H
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Floating Point Instructions FSQRT F
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Floating Point Instructions FSQRT F
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Floating Point Instructions FSUB Fl
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Floating Point Instructions FSUB Fl
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Floating Point Instructions FTAN Ta
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Floating Point Instructions FTAN Ta
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Floating Point Instructions FTANH H
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Floating Point Instructions FTENTOX
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Floating Point Instructions FTENTOX
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Floating Point Instructions FTRAPcc
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Floating Point Instructions FTST Te
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Floating Point Instructions FTWOTOX
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Floating Point Instructions FTWOTOX
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Supervisor (Privileged) Instruction
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CPU32 Instructions Addressing in th
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CPU32 Instructions BGND Operation:
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CPU32 Instructions TBLS TBLS TBLSN
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CPU32 Instructions TBLU TBLU TBLUN
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CPU32 Instructions TBLU TBLU TBLUN
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CPU32 Instructions 7-16 M68000 FAMI
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Instruction Format Summary 8.1.5 De
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Instruction Format Summary 8.1.8 Si
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Instruction Format Summary SUBI RTM
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Instruction Format Summary BCLR 8-8
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Instruction Format Summary MOVE fro
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Instruction Format Summary ILLEGAL
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Instruction Format Summary STOP 15
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Instruction Format Summary DBcc 15
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Instruction Format Summary SUBX 15
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Instruction Format Summary ADD ASL,
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Instruction Format Summary BFINS 15
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Instruction Format Summary PFLUSH P
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Instruction Format Summary PFLUSHR
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Instruction Format Summary MOVE16 A
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Instruction Format Summary FLOGNP1
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Instruction Format Summary FLOGN 15
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Instruction Format Summary FSGLMUL
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Instruction Format Summary FMOVE DA
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Instruction Format Summary cpRESTOR
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Instruction Format Summary 8-40 M68
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Processor Instruction Summary A-2 T
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Processor Instruction Summary Table
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Processor Instruction Summary A-10
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Processor Instruction Summary A.1 M
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Processor Instruction Summary A.1.2
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Processor Instruction Summary A.5 M
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APPENDIX B EXCEPTION PROCESSING REF
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B.2 EXCEPTION STACK FRAMES MOTOROLA
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MOTOROLA SP +$02 +$06 +$08 +$0C 15
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MOTOROLA SP +$02 +$06 +$08 +$0A +$0
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MOTOROLA 15 0 SP STATUS REGISTER +$
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Exception Processing Reference B-11
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B-13 MC68000 FAMILY PROGRAMMER’S
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S-Record Output Format When downloa
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S-Record Output Format The next 16
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