MOTOROLA M68000 FAMILY Programmer's Reference ... - Freescale

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Table 1-6. Extended-Precision Real Format Summary Data Format 95 94 80 79 64 63 62 0 s e z i f Field Size (in Bits) Sign (s) 1 Biased Exponent (e) 15 Zero, Reserved (u) 16 Explicit Integer Bit (j) 1 Mantissa (f) 63 Total 96 Interpretation of Unused Bits Input Don’t Care Output All Zeros Interpretation of Sign Positive Mantissa s = 0 Negative Mantissa s = 1 Normalized Numbers Bias of Biased Exponent +16383 ($3FFF) Range of Biased Exponent 0 < = e < 32767 ($7FFF) Explicit Integer Bit 1 Range of Mantissa Zero or Nonzero Mantissa (Explicit Integer Bit and Fraction ) 1.f Relation to Representation of Real Numbers (–1) s × 2 e–16383 × 1.f Denormalized Numbers Biased Exponent Format Minimum 0 ($0000) Bias of Biased Exponent +16383 ($3FFF) Explicit Integer Bit 0 Range of Mantissa Nonzero Mantissa (Explicit Integer Bit and Fraction ) 0.f Relation to Representation of Real Numbers (–1) s × 2– 16383 × 0.f Signed Zeros Biased Exponent Format Minimum 0 ($0000) Mantissa (Explicit Integer Bit and Fraction ) 0.0 Signed Infinities Biased Exponent Format Maximum 32767 ($7FFF) Explicit Integer Bit Don’t Care Mantissa (Explicit Integer Bit and Fraction ) x.000…0000 Introduction MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-23
Introduction Table 1-6. Extended-Precision Real Format Summary (Continued) NANs Sign Don’t Care Explicit Integer Bit Don’t Care Biased Exponent Format Maximum 32767 ($7FFF) Mantissa Representation of Fraction Nonzero Nonsignaling x.1xxxx…xxxx Signaling x.0xxxx…xxxx Nonzero Bit Pattern Created by User x.xxxxx…xxxx Fraction When Created by FPCP Approximate Ranges 1.11111…1111 Maximum Positive Normalized 1.2 × 104932 Minimum Positive Normalized 1.7 × 10 –4932 Minimum Positive Denormalized 3.7 × 10 4951 Table 1-7. Packed Decimal Real Format Summary 3-Digit 1-Digit Data Type SM SE Y Y Exponent Integer 16-Digit Fraction ±Infinity 0/1 1 1 1 $FFF $XXXX $00…00 ±NAN 0/1 1 1 1 $FFF $XXXX Nonzero ±SNAN 0/1 1 1 1 $FFF $XXXX Nonzero +Zero 0 0/1 X X $000–$999 $XXX0 $00…00 –Zero 1 0/1 X X $000–$999 $XXX0 $00…00 +In-Range 0 0/1 X X $000–$999 $XXX0–$XXX9 $00…01–$99…99 –In-Range 1 0/1 X X $000–$999 $XXX0–$XXX9 $00…01–$99…99 A packed decimal real data format with the SE and both Y bits set, an exponent of $FFF, and a nonzero 16-bit decimal fraction is a NAN. When the FPU uses this format, the fraction of the NAN is moved bit- by-bit into the extended-precision mantissa of a floating-point data register. The exponent of the register is set to signify a NAN, and no conversion occurs. The MSB of the most significant digit in the decimal fraction (the MSB of digit 15) is a don’t care, as in extended-precision NANs, and the MSB of minus one of digit 15 is the SNAN bit. If the NAN bit is a zero, then it is an SNAN. If a non-decimal digit ($A – $F) appears in the exponent of a zero, the number is a true zero. The FPU does not detect non-decimal digits in the exponent, integer, or fraction digits of an in-range packed decimal real data format. These non-decimal digits are converted to binary in the same manner as decimal digits; however, the result is probably useless although it is repeatable. Since an in-range number cannot overflow or underflow when converted to extended precision, conversion from the packed decimal real data format always produces normalized extended-precision numbers. 1-24 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Page 2 and 3: © MOTOROLA INC., 1992 MOTOROLA M68
Page 4 and 5: Paragraph Number iv TABLE OF CONTEN
Page 6 and 7: Paragraph Number vi TABLE OF CONTEN
Page 8 and 9: Figure Number MOTOROLA LIST OF FIGU
Page 10 and 11: Table Number MOTOROLA LIST OF TABLE
Page 12 and 13: SECTION 1 INTRODUCTION This manual
Page 14 and 15: 1.1.3 Program Counter MOTOROLA M680
Page 16 and 17: 1.2.2 Floating-Point Control Regist
Page 18 and 19: MOTOROLA M68000 FAMILY PROGRAMMER
Page 20 and 21: Registers MOTOROLA 68000 68008 68HC
Page 24 and 25: E—Enable 0 = Transparent translat
Page 26 and 27: 1.5 FLOATING-POINT DATA FORMATS MOT
Page 30 and 31: 1.6.3 Zeros Introduction Zeros can
Page 32 and 33: Table 1-4. Single-Precision Real Fo
Page 36 and 37: 1.7 ORGANIZATION OF DATA IN REGISTE
Page 38 and 39: Introduction Control registers vary
Page 40 and 41: BYTE n - 1 7 0 7 0 7 0 BYTE n - 1 A
Page 42 and 43: SECTION 2 ADDRESSING CAPABILITIES M
Page 44 and 45: MOTOROLA Table 2-1. Instruction Wor
Page 46 and 47: 2.2.1 Data Register Direct Mode MOT
Page 48 and 49: 2.2.5 Address Register Indirect wit
Page 52 and 53: 2.2.9 Memory Indirect Postindexed M
Page 54 and 55: 2.2.11 Program Counter Indirect wit
Page 58 and 59: 2.2.15 Program Counter Memory Indir
Page 60 and 61: 2.2.18 Immediate Data MOTOROLA M680
Page 62 and 63: 2.4 BRIEF EXTENSION WORD FORMAT COM
Page 64 and 65: A6 = 0 1 2 3 A6 = 0 A6 = 0 1 SIMPLE
Page 66 and 67: 2.5.2 Memory Indirect Modes Address
Page 68 and 69: . Addressing Capabilities 2.5.2.3 M
Page 70 and 71: Addressing Capabilities To implemen
Page 72 and 73: SECTION 3 INSTRUCTION SET SUMMARY T
Page 74 and 75: MOTOROLA Table 3-1. Notational Conv
Page 76 and 77: 3.1.1 Data Movement Instructions MO
Page 80 and 81: Table 3-5. Shift and Rotate Operati
Page 82 and 83: 3.1.7 Binary-Coded Decimal Instruct
Page 84 and 85:
Table 3-10. System Control Operatio
Page 86 and 87:
3.1.12 Memory Management Unit (MMU)
Page 88 and 89:
Table 3-17. Monadic Floating-Point
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LSR (r = 0) — * * 0 0 ROXL (r = 0
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Instruction Set Summary extends the
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3.5 FLOATING-POINT COMPUTATIONAL AC
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3.5.2 Rounding the Result Instructi
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Instruction Set Summary intermediat
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Table 3-22. FPCC Encodings Data Typ
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Table 3-23. Floating-Point Conditio
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INSTRUCTION NAME APPLICABLE PROCESS
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Integer Instructions ABCD Operation
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Integer Instructions ADD Operation:
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Integer Instructions ADD 4-6 Add (M
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Integer Instructions ADDA 4-8 Add A
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Integer Instructions ADDI Add Immed
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Integer Instructions ADDQ Add Quick
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Integer Instructions ADDX Add Exten
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Integer Instructions AND AND Logica
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Integer Instructions ANDI AND Immed
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Integer Instructions ANDI ANDI to C
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Integer Instructions ASL, ASR Arith
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Integer Instructions ASL, ASR Arith
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Integer Instructions Bcc Branch Con
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Integer Instructions BCHG Test a Bi
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Integer Instructions BCLR Test a Bi
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Integer Instructions BCLR Test a Bi
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Integer Instructions BFCHG Test Bit
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Integer Instructions BFCLR Test Bit
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Integer Instructions BFEXTS Extract
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Integer Instructions BFEXTU Extract
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Integer Instructions BFEXTU Extract
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Integer Instructions BFFFO Find Fir
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Integer Instructions BFINS Insert B
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Integer Instructions BFINS Insert B
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Integer Instructions BFSET Test Bit
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Integer Instructions BFTST Test Bit
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Integer Instructions BKPT Breakpoin
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Integer Instructions BSET Test a Bi
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Integer Instructions BSET Test a Bi
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Integer Instructions BSR Branch to
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Integer Instructions BTST Test a Bi
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Integer Instructions CALLM Call Mod
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Integer Instructions CAS CAS CAS2 C
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Integer Instructions CAS CAS CAS2 C
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Integer Instructions CHK Check Regi
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Integer Instructions CHK2 Check Reg
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Integer Instructions CLR Clear an O
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Integer Instructions CMP Compare CM
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Integer Instructions CMPA Compare A
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Integer Instructions CMPI Compare I
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Integer Instructions CMP2 Compare R
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Integer Instructions cpBcc Branch o
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Integer Instructions cpGEN Coproces
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Integer Instructions cpScc Set on C
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Integer Instructions DBcc Test Cond
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Integer Instructions DIVS, DIVSL Si
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Integer Instructions DIVS, DIVSL Si
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Integer Instructions DIVU, DIVUL Un
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Integer Instructions DIVU, DIVUL Un
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Integer Instructions EOR Exclusive-
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Integer Instructions EORI Exclusive
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Integer Instructions EORI EORI to C
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Integer Instructions EXT, EXTB Sign
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Integer Instructions JMP Jump JMP (
Page 214 and 215:
Integer Instructions LEA Load Effec
Page 216 and 217:
Integer Instructions LINK Link and
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Integer Instructions LSL, LSR Logic
Page 220 and 221:
Integer Instructions MOVE Move Data
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Integer Instructions MOVE Move Data
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Integer Instructions MOVEA Move Add
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Integer Instructions MOVE MOVE from
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Integer Instructions MOVE MOVE to C
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Integer Instructions MOVE16 Move 16
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Integer Instructions MOVEM Move Mul
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Integer Instructions MOVEM Move Mul
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Integer Instructions MOVEP Move Per
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Integer Instructions MOVEQ Move Qui
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Integer Instructions MULS Signed Mu
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Integer Instructions MULU Unsigned
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Integer Instructions MULU Unsigned
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Integer Instructions NBCD Negate De
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Integer Instructions NEG Negate NEG
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Integer Instructions NEGX Negate wi
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Integer Instructions NOT Logical Co
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Integer Instructions OR Inclusive-O
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Integer Instructions OR Inclusive-O
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Integer Instructions ORI Inclusive-
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Integer Instructions PACK Pack PACK
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Integer Instructions PACK Pack PACK
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Integer Instructions ROL, ROR Rotat
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Integer Instructions ROL, ROR Rotat
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Integer Instructions ROXL, ROXR Rot
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Integer Instructions RTD Return and
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Integer Instructions RTR Return and
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Integer Instructions SBCD Subtract
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Integer Instructions Scc Set Accord
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Integer Instructions SUB Subtract S
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Integer Instructions SUB Subtract S
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Integer Instructions SUBA Subtract
Page 284 and 285:
Integer Instructions SUBI Subtract
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Integer Instructions SUBQ Subtract
Page 288 and 289:
Integer Instructions SUBX Subtract
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Integer Instructions TAS Test and S
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Integer Instructions TRAP Trap TRAP
Page 294 and 295:
Integer Instructions TRAPcc Trap on
Page 296 and 297:
Integer Instructions TST Test an Op
Page 298 and 299:
Integer Instructions UNLK Unlink UN
Page 300 and 301:
Integer Instructions UNPK Unpack BC
Page 302 and 303:
Integer Instructions 4-198 M68000 F
Page 304 and 305:
Floating Point Instructions 5-2 Tab
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Floating Point Instructions FABS Op
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Floating Point Instructions FABS In
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Floating Point Instructions FACOS O
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Floating Point Instructions FACOS 5
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Floating Point Instructions FADD Fl
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Floating Point Instructions FASIN A
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Floating Point Instructions FASIN A
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Floating Point Instructions FATAN A
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Floating Point Instructions FATANH
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Floating Point Instructions FATANH
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Floating Point Instructions FBcc Fl
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Floating Point Instructions FCMP Fl
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Floating Point Instructions FCOS Co
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Floating Point Instructions FCOS Co
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Floating Point Instructions FCOSH H
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Floating Point Instructions FDBcc F
Page 338 and 339:
Floating Point Instructions FDIV Fl
Page 340 and 341:
Floating Point Instructions FDIV Fl
Page 342 and 343:
Floating Point Instructions FETOX e
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Floating Point Instructions FETOX e
Page 346 and 347:
Floating Point Instructions FETOXM1
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Floating Point Instructions FGETEXP
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Floating Point Instructions FGETEXP
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Floating Point Instructions FGETMAN
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Floating Point Instructions FINT In
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Floating Point Instructions FINT In
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Floating Point Instructions FINTRZ
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Floating Point Instructions FLOG10
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Floating Point Instructions FLOG10
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Floating Point Instructions FLOG2 L
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Floating Point Instructions FLOGN L
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Floating Point Instructions FLOGN L
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Floating Point Instructions FLOGNP1
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Floating Point Instructions FMOD Mo
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Floating Point Instructions FMOD Mo
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Floating Point Instructions FMOVE M
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Floating Point Instructions FMOVECR
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Floating Point Instructions FMOVEM
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Floating Point Instructions FMUL Fl
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Floating Point Instructions FMUL Fl
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Floating Point Instructions FNEG Fl
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Floating Point Instructions FNEG Fl
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Floating Point Instructions FNOP No
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Floating Point Instructions FREM IE
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Floating Point Instructions FREM IE
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Floating Point Instructions FSCALE
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Floating Point Instructions FScc Se
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Floating Point Instructions FSGLDIV
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Floating Point Instructions FSGLDIV
Page 418 and 419:
Floating Point Instructions FSGLMUL
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Floating Point Instructions FSIN Si
Page 422 and 423:
Floating Point Instructions FSIN Si
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Floating Point Instructions FSINCOS
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Floating Point Instructions FSINCOS
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Floating Point Instructions FSINH H
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Floating Point Instructions FSQRT F
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Floating Point Instructions FSQRT F
Page 434 and 435:
Floating Point Instructions FSUB Fl
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Floating Point Instructions FSUB Fl
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Floating Point Instructions FTAN Ta
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Floating Point Instructions FTAN Ta
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Floating Point Instructions FTANH H
Page 444 and 445:
Floating Point Instructions FTENTOX
Page 446 and 447:
Floating Point Instructions FTENTOX
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Floating Point Instructions FTRAPcc
Page 450 and 451:
Floating Point Instructions FTST Te
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Floating Point Instructions FTWOTOX
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Floating Point Instructions FTWOTOX
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Supervisor (Privileged) Instruction
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CPU32 Instructions Addressing in th
Page 544 and 545:
CPU32 Instructions BGND Operation:
Page 546 and 547:
CPU32 Instructions TBLS TBLS TBLSN
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CPU32 Instructions TBLU TBLU TBLUN
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CPU32 Instructions TBLU TBLU TBLUN
Page 556 and 557:
CPU32 Instructions 7-16 M68000 FAMI
Page 558 and 559:
Instruction Format Summary 8.1.5 De
Page 560 and 561:
Instruction Format Summary 8.1.8 Si
Page 562 and 563:
Instruction Format Summary SUBI RTM
Page 564 and 565:
Instruction Format Summary BCLR 8-8
Page 566 and 567:
Instruction Format Summary MOVE fro
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Instruction Format Summary ILLEGAL
Page 570 and 571:
Instruction Format Summary STOP 15
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Instruction Format Summary DBcc 15
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Instruction Format Summary SUBX 15
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Instruction Format Summary ADD ASL,
Page 578 and 579:
Instruction Format Summary BFINS 15
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Instruction Format Summary PFLUSH P
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Instruction Format Summary PFLUSHR
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Instruction Format Summary MOVE16 A
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Instruction Format Summary FLOGNP1
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Instruction Format Summary FLOGN 15
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Instruction Format Summary FSGLMUL
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Instruction Format Summary FMOVE DA
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Instruction Format Summary cpRESTOR
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Instruction Format Summary 8-40 M68
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Processor Instruction Summary A-2 T
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Processor Instruction Summary Table
Page 606 and 607:
Processor Instruction Summary A-10
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Processor Instruction Summary A.1 M
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Processor Instruction Summary A.1.2
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Processor Instruction Summary A.5 M
Page 628 and 629:
APPENDIX B EXCEPTION PROCESSING REF
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B.2 EXCEPTION STACK FRAMES MOTOROLA
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MOTOROLA SP +$02 +$06 +$08 +$0C 15
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MOTOROLA SP +$02 +$06 +$08 +$0A +$0
Page 636 and 637:
MOTOROLA 15 0 SP STATUS REGISTER +$
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Exception Processing Reference B-11
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B-13 MC68000 FAMILY PROGRAMMER’S
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S-Record Output Format When downloa
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S-Record Output Format The next 16
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