MOTOROLA M68000 FAMILY Programmer's Reference ... - Freescale

MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Introduction
supported, where T0 is always zero, and only one system stack where the M-bit is always
zero. I2, I1, and I0 define the interrupt mask level.
T1 T0 S M 0 I2 I1 I0 0 0 0 X N Z V C
TRACE
ENABLE
SUPERVISOR/USER STATE
SYSTEM BYTE
1.3.3 Vector Base Register (VBR)
.
INTERRUPT
PRIORITY MASK
Figure 1-8. Status Register
The VBR contains the base address of the exception vector table in memory. The
displacement of an exception vector adds to the value in this register, which accesses the
vector table.
1.3.4 Alternate Function Code Registers (SFC and DFC)
The alternate function code registers contain 3-bit function codes. Function codes can be
considered extensions of the 32-bit logical address that optionally provides as many as eight
4-Gbyte address spaces. The processor automatically generates function codes to select
address spaces for data and programs at the user and supervisor modes. Certain
instructions use SFC and DFC to specify the function codes for operations.
1.3.5 Acu Status Register (MC68EC030 only)
USER BYTE
(CONDITION CODE REGISTER)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVERFLOW
NEGATIVE
MASTER/INTERRUPT STATE EXTEND
T1 T0
0 0
1 0
0 1
1 1
TRACE MODE
NO TRACE
TRACE ON ANY INSTRUCTION
TRACE ON CHANGE OF FLOW
UNDEFINED
S M
0 x
1 0
1 1
ACTIVE STACK
The access control unit status register (ACUSR) is a 16-bit register containing the status
information returned by execution of the PTEST instruction. The PTEST instruction
searches the access control (AC) registers to determine a match for a specified address. A
match in either or both of the AC registers sets bit 6 in the ACUSR. All other bits in the
ACUSR are undefined and must not be used.
USP
ISP
MSP
CARRY
ZERO
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