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$Diffraction Grating Effect on Waveguided Germanium MSM ...$

Cover Story regime (1.3~1.55μm), germanium (Ge) could be exploited as alternative for the realization of high performance photodetector due to its favourable absorption coefficient. However, Ge can be a challenging material to integrate in a CMOS environment for its low thermal budget constraint and its large lattice mismatch of ~4.2% with Si [1]. High defect densities seen in the Ge-on-Siliconon- Insulator (Ge-on-SOI) epitaxial film could induce unfavourable carrier recombination process that would degrade the detector’s quantum efficiency. Development of Hetero-Epitaxy of Germanium on Silicon Figure 1: Schematic illustration of on-chip optical interconnects realized using a photonics integrated circuit platform. circuit using an electrical power supply, a high quantum efficiency laser source is employed to provide the required optical power in a photonics integrated circuit. By leveraging on the high index contrast between the Si core and the silicon-dioxide cladding, routing of optical signals using photonic waveguide with low propagation loss can be made possible. To harness increased data capacity, a wavelength division multiplexing (WDM) based on arrayedwaveguide grating (AWG) composed of rib SOI waveguides or ring resonator in photonic domain can be exploited to provide multiple channels transmission for parallel data processing. Using an optical filter, a particular wavelength (λ n ) can be selected into the photonic waveguide data bus. While Si-based modulator exhibits weaker electrooptical coefficients due to its central symmetry in the lattice structure, a free carrier plasma dispersion effect can be exploited to enable effective optical modulation. The modulated optical signals are channelled through the photonic waveguide data bus where multiple wavelengths signals can be delivered on the same channel without suffering interference from one another. At the receiving end, signal of a specific wavelength channel is filtered and fed into a photodetector for enabling opticalto-electrical encoding. The encoded electrical signal will then pass through the CMOS circuitry for data processing. Although it appears promising that an electronic-photonic integration could enable the convergence of computing and communication capabilities on single ship platform, its wide spread implementation has been hindered by the grand challenge in demonstrating an important active photonic component needed to perform opto-electric (OE) signal conversion. The search for a new material that is compatible with the mainstream CMOS process technology is of particular interest. While silicon (Si) has been shown to be unsuitable for optical detection in the near-infrared wavelength The key challenge to high quality germanium (Ge) epitaxy growth on silicon (Si) rests with the huge lattice mismatch between the two heterostructure materials. The existence of ~4.2% lattice mismatch strain has been shown to give rise to two major issues: (1) high densities of threading dislocations and (2) rough surface morphology due to 3D Stranski-Krastanov (SK) growth. Both of these defects present much concerns for the generation of high leakage current which would compromise the efficiency of a photodetector. Strategies proposed in the literature to overcome these challenges vary to a large extent. Colace et al. proposed a direct heteroepitaxy growth of Ge on Si through the use of a low temperature thin SiGe buffer layer (a few 10nm) [2]. The insertion of such thin buffer avoids the occurrence of 3D SK growth and allows the misfit dislocations to be concentrated at the hetero-interfaces. However such approach requires a cyclic annealing process to be carried out at both high and low temperature (900°C/780°C) to reduce the threading dislocation density within the Ge active film. Using a similar cyclic thermal annealing approach, Luan et al. had also demonstrated a significant improvement in both the surface roughness and the dislocation density [1]. Unfortunately, the needs for a high temperature post-epitaxy Ge anneal with long cycle time present a major concern for CMOS implementation. 4 Institute of Microelectronics
Cover Story In our approach, selective epitaxial growth of Ge on silicon-on-insulator (SOI) was performed using an ultra-high vacuum chemical vapor deposition reactor [3]-[13]. Unlike the conventional approaches, a thin pseudo-graded SiGe buffer with a thickness of ~20nm is proposed in this study to relieve the large lattice mismatch stress between the two heterostructure materials (Figure 2). The Ge mole fraction within the SiGe buffer is compositionally graded from 10% to ~50%. The precursor gases used for the SiGe growth comprise of diluted germane (GeH 4 ) and pure disilane (Si 2 H 6 ). A relatively thin Ge seed layer of ~30nm is subsequently grown on the SiGe buffer at a process temperature of 370°C. The use of a low temperature growth is intended to suppress adatoms migration on Si and thus prevents the formation of 3D SK growth, which allows a flat Ge surface morphology to be achieved. Upon obtaining a smooth Ge seed layer, the epitaxy process temperature is then increased to ~550°C to facilitate faster epitaxy growth to obtain the desired Ge thickness. Using this approach, high quality Ge epilayer with a thickness of up to ~2μm has been demonstrated, along with the achievement of threading dislocation density as low as ~107 cm -2 without undergoing any high temperature cyclical thermal annealing step. In addition, selective area growth of Ge on Si has also been developed using a cyclical deposition and etch back approach. In each deposition cycle, the Ge growth time is carefully optimized to avoid exceeding the incubation time needed for Ge seeds to nucleate on the dielectric film. After every Ge deposition cycle, a short etch back process using chlorine (Cl 2 ) precursor gas is then introduced to remove possible Ge nucleation sites on the dielectric. This allows a highly selective Ge epitaxy process to be developed, along with the achievement of excellent surface roughness of ~0.28nm. Waveguided Ge Photodetector Platform Technology For future realization of ultra-compact photonics integrated circuit, the integration of Ge photodetector with optical waveguide and the demonstration of high sensitivity with thin Ge epilayer (
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