Two very different approaches to MEMS packaging - I-Micronews

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F e b r u a r y 2 0 1 3
The company expects stacking of chips with wire
bonding to continue to be its main approach even as
sensors move increasingly to multichip combinations
in single packages, that integrate some combination
of accelerometers, gyroscopes, and magnetometers
for full motion sensing, plus a microcontroller for
more sophisticated processing and perhaps a RF
chip for wireless. That means more thinning of the
chips — of the CMOS more readily than the more
sensitive MEMS — for triple stacking to still stay
under the 1mm package height limit expected for
mobile consumer products. “Our roadmap is that
the standard LGA works fine,” says Schaefer, arguing
that direct wafer-to-wafer or chip-to-wafer bonding
or bumping won’t work well with multiple chips of
very different sizes. “And TSV is too expensive,” he
notes. “We’re still fine with wire bonding.”
On the automotive side, customers are discussing
alternatives to SOIC packages, but concern for
the reliability of the soldering in smaller packages
outweighs the limited interest in reducing size. Here
too the main emphasis is on pushing the conventional
technology, to eliminate pre-mold and optimize the
molding compound and process specifications.
Bosch has, however, recently made its first foray
into wafer-level chip sized packaging, with its
latest tiny 3-axis magnetometer. The magnetic
sensor elements are integrated into the ASIC and
solder bumps added on top. The combination of
ASIC and solder bumps has a height of 0.6mm.
“This is our only WL CSP so far without any mold,”
notes Bischopink, suggesting some caution about
how widely applicable the technology will be, as it
requires more robust sensors than for an LGA.
Silex pushes low-density TSVs
to next generation
At the other end of the spectrum, the leading pureplay
MEMS foundry Silex Microsystems has seen
double digit growth in recent years, to close to
$40 million in annual sales, in large part by providing
its small fabless MEMS customers with an established
through-silicon via interconnect to distinguish their
products. Peter Himes, Silex VP of marketing and
strategic alliances, says that about half its customers
now use its low density, all-silicon TSV process,
either for an interposer between the MEMS and ASIC
chips, or as an element of the MEMS for its I/O to
the ASIC or the board, allowing reduction of the pad
area for smaller, lower cost devices. These via-first
connections are made in full-thickness wafers by
isolating plugs of low-resistance silicon by etching
around them and filling the trench with dielectric.
TSVs for MEMS are generally low density, with typical
pitches of 100 to 200µm and anywhere from 2 to 20
TSVs per device, on full-thickness wafers that avoid
the need for thin wafer handling or special carriers,
a much simpler and lower cost solution than the thin
interposers for high density ICs.
The Swedish company is now introducing a new
generation of copper-filled vias in full thickness
wafers, pushing the low-density TSV approach
towards smaller pitch and lower resistance, to extend
application to smaller MEMS devices, and potentially
to other analog, mixed signal, LED and power devices
that also need 10s or 100s, not 1000s of vias. These
90µm-diameter copper vias use technology licensed
from Swedish supplier ÅAC Microtec. A small etch
from the front and a deep etch from the back create
a waist in the middle of the full-wafer via profile that
serves as a locking pin to prevent the relatively large
plug from popping out during temperature cycling.
The copper filling has a hollow core to compensate
for the TCE mismatch between the copper and the
silicon to improve reliability.
Next on the roadmap is a 50µm version, and a
technology to build embedded passives into the
silicon along with the copper vias, developed in
conjunction with an European-funded research
program. An inductor, for example, could be built
through the vertical TSV to take up less substrate
surface area than the usual horizontal coil, providing
high inductance-per-unit-area integrated passive
capabilities.
Silex is currently working to develop complete
characterization of the thermal and frequency and
other properties for the final packaging and assembly
of these wafer-level TSV stacks, to offer customers a
complete engineered solution of the whole system to
ease design and speed transfer to production of the
packaged device.
Paula Doe for Yole Développement
(Courtesy of Silex Microsystems)
“Our roadmap is
that the standard
LGA works fine.
We’re still fine with
wire bonding,”
says Dr Frank
Schaefer, Bosch.
Dr. Georg Bischopink, Vice
President, Bosch Engineering
Sensors for External Customers
and Sensor Packages, Bosch
Georg hold in 1992 a Ph. D. in
semiconductor physics, University
of Freiburg, Germany. He has
worked at Bosch since 1992 at various positions such as
Section Manager - Development MEMS Sensor Products,
Director, Bosch MEMS-Production or Vice President, Bosch
Corporate Research Microsystem-Technology.
Peter Himes, VP Marketing
& Strategic Alliances, Silex
Microsystems
Peter has over 25 years’ experience
in helping startups and public
companies establish their strategic
direction and industry position.
Experienced in IC and MEMS alike,
Peter has held VP of Sales and/or Marketing positions
at QuickSil, SiTime, and Winbond Corporations.
Dr. Frank Schaefer, Senior
Manager for Product
Management Automotive
MEMS, Bosch
Franck hold in 1999 a Ph.D. in
semiconductor physics, University
of Wuerzburg, Germany. He has
been working with Bosch since 1999 at various positions
in the field of MEMS. Since 2012, he is head of product
management for automotive MEMS sensors.
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