Two very different approaches to MEMS packaging - I-Micronews

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I S S U E N ° 2 6 F e b r u a r y 2 0 1 3 The company expects stacking of chips with wire bonding to continue to be its main approach even as sensors move increasingly to multichip combinations in single packages, that integrate some combination of accelerometers, gyroscopes, and magnetometers for full motion sensing, plus a microcontroller for more sophisticated processing and perhaps a RF chip for wireless. That means more thinning of the chips — of the CMOS more readily than the more sensitive MEMS — for triple stacking to still stay under the 1mm package height limit expected for mobile consumer products. “Our roadmap is that the standard LGA works fine,” says Schaefer, arguing that direct wafer-to-wafer or chip-to-wafer bonding or bumping won’t work well with multiple chips of very different sizes. “And TSV is too expensive,” he notes. “We’re still fine with wire bonding.” On the automotive side, customers are discussing alternatives to SOIC packages, but concern for the reliability of the soldering in smaller packages outweighs the limited interest in reducing size. Here too the main emphasis is on pushing the conventional technology, to eliminate pre-mold and optimize the molding compound and process specifications. Bosch has, however, recently made its first foray into wafer-level chip sized packaging, with its latest tiny 3-axis magnetometer. The magnetic sensor elements are integrated into the ASIC and solder bumps added on top. The combination of ASIC and solder bumps has a height of 0.6mm. “This is our only WL CSP so far without any mold,” notes Bischopink, suggesting some caution about how widely applicable the technology will be, as it requires more robust sensors than for an LGA. Silex pushes low-density TSVs to next generation At the other end of the spectrum, the leading pureplay MEMS foundry Silex Microsystems has seen double digit growth in recent years, to close to $40 million in annual sales, in large part by providing its small fabless MEMS customers with an established through-silicon via interconnect to distinguish their products. Peter Himes, Silex VP of marketing and strategic alliances, says that about half its customers now use its low density, all-silicon TSV process, either for an interposer between the MEMS and ASIC chips, or as an element of the MEMS for its I/O to the ASIC or the board, allowing reduction of the pad area for smaller, lower cost devices. These via-first connections are made in full-thickness wafers by isolating plugs of low-resistance silicon by etching around them and filling the trench with dielectric. TSVs for MEMS are generally low density, with typical pitches of 100 to 200µm and anywhere from 2 to 20 TSVs per device, on full-thickness wafers that avoid the need for thin wafer handling or special carriers, a much simpler and lower cost solution than the thin interposers for high density ICs. The Swedish company is now introducing a new generation of copper-filled vias in full thickness wafers, pushing the low-density TSV approach towards smaller pitch and lower resistance, to extend application to smaller MEMS devices, and potentially to other analog, mixed signal, LED and power devices that also need 10s or 100s, not 1000s of vias. These 90µm-diameter copper vias use technology licensed from Swedish supplier ÅAC Microtec. A small etch from the front and a deep etch from the back create a waist in the middle of the full-wafer via profile that serves as a locking pin to prevent the relatively large plug from popping out during temperature cycling. The copper filling has a hollow core to compensate for the TCE mismatch between the copper and the silicon to improve reliability. Next on the roadmap is a 50µm version, and a technology to build embedded passives into the silicon along with the copper vias, developed in conjunction with an European-funded research program. An inductor, for example, could be built through the vertical TSV to take up less substrate surface area than the usual horizontal coil, providing high inductance-per-unit-area integrated passive capabilities. Silex is currently working to develop complete characterization of the thermal and frequency and other properties for the final packaging and assembly of these wafer-level TSV stacks, to offer customers a complete engineered solution of the whole system to ease design and speed transfer to production of the packaged device. Paula Doe for Yole Développement (Courtesy of Silex Microsystems) “Our roadmap is that the standard LGA works fine. We’re still fine with wire bonding,” says Dr Frank Schaefer, Bosch. Dr. Georg Bischopink, Vice President, Bosch Engineering Sensors for External Customers and Sensor Packages, Bosch Georg hold in 1992 a Ph. D. in semiconductor physics, University of Freiburg, Germany. He has worked at Bosch since 1992 at various positions such as Section Manager - Development MEMS Sensor Products, Director, Bosch MEMS-Production or Vice President, Bosch Corporate Research Microsystem-Technology. Peter Himes, VP Marketing & Strategic Alliances, Silex Microsystems Peter has over 25 years’ experience in helping startups and public companies establish their strategic direction and industry position. Experienced in IC and MEMS alike, Peter has held VP of Sales and/or Marketing positions at QuickSil, SiTime, and Winbond Corporations. Dr. Frank Schaefer, Senior Manager for Product Management Automotive MEMS, Bosch Franck hold in 1999 a Ph.D. in semiconductor physics, University of Wuerzburg, Germany. He has been working with Bosch since 1999 at various positions in the field of MEMS. Since 2012, he is head of product management for automotive MEMS sensors. 3 D P a c k a g i n g 7
F e b r u a r y 2 0 1 3 I S S U E N ° 2 6 “Instead of putting the high value ASIC on a blank silicon interposer with vias and interconnects, we could put the photonics on the interposer and connect it directly to the upstairs die,” says Chris Bergey, Luxtera. INDUSTRY REVIEW – FOCUS ON SILICON PHOTONICS PACKAGING Silicon photonics looks for 2.5D assembly at OSATs Though silicon photonics has so far relied on one-chip integration of optics with electronics to start to get real traction in the data communications market, sector pioneer Luxtera sees the evolving packaging technology for heterogeneous 2.5D integration as the next generation solution to scale integrated photonics to high volume production. The company is working to build up a scalable back end silicon photonics infrastructure with OSATs and assembly and test tool suppliers. Silicon photonics is still a small emerging market, but growing demand for high speed data communication is starting to spur serious interest. Yole Développement sees silicon photonic systems sales of some $215 million by 2017. The sector got a recent boost when Facebook announced plans to move to silicon photonics for its server interconnect, to enable disaggregation of computing into separate units for more efficient sharing of memory among multiple processors. Leading supplier Luxtera says it has shipped more than half a million of the optics-and-transistors-on-silicon devices to date, primarily for active optical cables in data centers, and sees demand for >10M units a year by 2016. One key enabler of this growth will be moving from the electrical system-on-a-chip approach to an electrical and optical system in a package solution, made possible by the recent advances in 3D packaging technology. “The silicon infrastructure’s development of 2.5D heterogeneous integration is a key technology path forward for photonics,” says Chris Bergey, Luxtera VP of marketing. “Instead of putting the high value ASIC on a blank silicon interposer with vias and interconnects, we could put the photonics on the interposer and connect it directly to the upstairs die. This allows the silicon to have optical I/O with much lower system power consumption, terabits of speed and >100 meters of reach.” Cisco Systems recently similarly announced that it was prototyping such a 2.5D silicon interposer solution. Integrating optics into electronics for higher speed transmission requires optical waveguides, modulators and receivers in silicon, integrated with CMOS transistors, which silicon photonics suppliers now make on a single chip. More complicated is getting the optical power supply of light into the system, whether by also integrating III-V laser devices into the silicon, or bonding on the compound semiconductor devices, or micro packaging a MEMS mirror device on top, or by connecting a separate laser component to the chip by optical fiber. Getting the light out of the system means connecting the chip to optical fiber. Integrating the diverse optics and electronics at the package level could be a simpler volume production solution, now that 2.5D heterogeneous integration technology for short, fast connections is emerging. A silicon photonics foundry could process the large photonic device, making waveguides, modulators, receivers, optical I/Os to connect to the ASIC, and Optical coupler: interfaces between interposer and MT-ferrules Optical fibers provide high-speed interconnect and provide supply of DC light to transmitters Photonic Interposer Package Substrate: • High & low speed IO • Power supply and • Mechanical support to interposer Heat sink mounted on package MT-Ferrules as example for pluggable fiber (MCF) interconnect Optical ASIC foor plan & packaging. (Courtesy of Luxtera) 8 3 D P a c k a g i n g
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Two very different approaches to MEMS packaging - I-Micronews

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