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Graph Processing & Bulk Synchronous Parallel Model

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Pregel <br />

• Input: A directed graph G. <br />

Each vertex is associated with an id and a value. <br />

Edges may also contain values. <br />

• Edges are not a first class ciFzen – they have no associated <br />

computaFon <br />

– VerFces can modify its state/edge state/edge set <br />

• ComputaFon finishes when <br />

ciently<br />

all verFces enter the inacFve state <br />

erant platform with an API that is su<br />

xpress arbitrary graph algorithms. This paper<br />

e resulting system, called Pregel 1 , and reports<br />

ce with it.<br />

evel organization of Pregel programs is inspired<br />

<strong>Bulk</strong> <strong>Synchronous</strong> <strong>Parallel</strong> model [45]. Pregel<br />

s consist of a sequence of iterations, called suring<br />

a superstep the framework invokes a usertion<br />

for each Lecture vertex, 14 : conceptually 590.02 Spring in 13 parallel. <br />

specifies behavior at a single vertex V and a<br />

Vote to halt<br />

Active<br />

Inactive<br />

Message received<br />

Figure 1: Vertex State Machine<br />

12

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