Xilinx UG393 Spartan-6 FPGA PCB Design Guide
Xilinx UG393 Spartan-6 FPGA PCB Design Guide
Xilinx UG393 Spartan-6 FPGA PCB Design Guide
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Chapter 2: Power Distribution System<br />
Figure 2-9 shows an averaged noise measurement taken at the V CCO pins of a sample<br />
design. In this case, the trigger was the clock for an I/O bus interface sending a 1-0-1-0<br />
pattern at 250 Mb/s.<br />
X-Ref Target - Figure 2-9<br />
ug393_c2_09_091809<br />
Figure 2-9:<br />
Averaged Measurement of V CCO Supply with Multiple I/O Sending<br />
Patterns at 250 Mb/s<br />
34 www.xilinx.com <strong>Spartan</strong>-6 <strong>FPGA</strong> <strong>PCB</strong> <strong>Design</strong> and Pin Planning<br />
<strong>UG393</strong> (v1.1) April 29, 2010
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