Xilinx UG393 Spartan-6 FPGA PCB Design Guide

Chapter 4: PCB Materials and Traces
X-Ref Target - Figure 4-1
d=2h+t
h
h
w
s
w
t
Er
UG393_c4_01_091809
Figure 4-1:
Differential Edge-Coupled Centered Stripline
X-Ref Target - Figure 4-2
h
orthogonal lines
t
d=3h+2t
h
h
w
s
w
t
Er
UG393_c4_02_091809
Figure 4-2:
Differential Edge-Coupled Offset Stripline
X-Ref Target - Figure 4-3
t
h
w
Er
d=4h+2t
2h
h
t
UG393_c4_03_091809
Figure 4-3:
Centered Broadside-Coupled Stripline
X-Ref Target - Figure 4-4
t
w
s
w
Er = 1
h
Er
UG393_c4_04_091809
Figure 4-4:
Differential Microstrip
A good PCB manufacturer understands controlled impedance and allows fine adjustments
for line widths to produce a Z 0O of 50Ω . The PCB manufacturer also provides the
parameters necessary for the specific PCB layout. Some parameters can be calculated or
simulated from the guideline outlined in the example. Although ±10% tolerance on Z 0O is
typical and can provide adequate performance, the additional cost of a tighter tolerance
results in better channel performance.
44 www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010