TSV technology for large die Cu/low K chip packaging
TSV technology for large die Cu/low K chip packaging
TSV technology for large die Cu/low K chip packaging
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Packaging with Si carrier & <strong>TSV</strong><br />
(Source : Eric Beyne, IMEC)<br />
Source: IME’s Si stacked module (2005)<br />
(Ref : Knickerbocker, IBM J. Res & Dev, 2005)<br />
(Source : Intel, US)<br />
Silicon carrier with <strong>TSV</strong> is emerging solution <strong>for</strong> high per<strong>for</strong>mance integration plat<strong>for</strong>m
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