A Digital Backend Architecture for Fourier Imaging
A Digital Backend Architecture for Fourier Imaging
A Digital Backend Architecture for Fourier Imaging
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40 Mbps<br />
ADC<br />
64ch<br />
16 out x 4 ch each x 12 bit<br />
13<br />
16ch x 12 bit<br />
(32ch interleaved)<br />
0 - 3<br />
4 - 7<br />
Ant0<br />
Ch0<br />
Ant4<br />
Ch0<br />
Ant1<br />
Ch0<br />
Ant5<br />
Ch0<br />
Ant2<br />
Ch0<br />
Ant6<br />
Ch0<br />
Ant3<br />
Ch0<br />
Ant7<br />
Ch0<br />
Ant0<br />
Ch1<br />
Ant4<br />
Ch1<br />
Ant1<br />
Ch1<br />
Ant5<br />
Ch1<br />
dout0<br />
dout1<br />
The 64 input AD takes both the ZDOKs connector<br />
on the ROACH board, there is a supply connector<br />
to allow to plug 64 SMA connectors<br />
F engine