A Digital Backend Architecture for Fourier Imaging

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S engine data order t 2^20 t 3072 t 2048 t 1024 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 a7c1023 a0c3 a0c2 a0c1 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 a15c1023 a8c3 a8c2 a8c1 a9 a8 a15 a14 a13 a12 a11 a10 a9 a8 a23c1023 a16c3 a16c2 a16c1 a17 a16 a23 a22 a21 a20 a19 a18 a17 a16 a31c1023 a24c3 a24c2 a24c1 a25 a24 a31 a30 a29 a28 a27 a26 a25 a24 47 Considering the original number the S-engine will receive data in this order FFT real output sequence New numbering Prefix 0-4-1-5-2-6-3-7 0-1-2-3-4-5-6-7 0-7 8_12_9_13_10_14_11_15 8-9-10-11-12-13-14-15 8-15 16_20_17_21_18_22_19_23 16-17-18-19-20-21-22-23 16-23 24_28_25_29_26_30_27_31 24-25-26-27-28-29-30-31 24-31 F engine
S engine data order t 2^20 t 3072 t 2048 t 1024 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 a7c1023 a0c3 a0c2 a0c1 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 a15c1023 a8c3 a8c2 a8c1 a9 a8 a15 a14 a13 a12 a11 a10 a9 a8 a23c1023 a16c3 a16c2 a16c1 a17 a16 a23 a22 a21 a20 a19 a18 a17 a16 a31c1023 a24c3 a24c2 a24c1 a25 a24 a31 a30 a29 a28 a27 a26 a25 a24 the final sequence is 48 t 2^20 t 3072 t 2048 t 1024 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 a7c1023 a0c3 a0c2 a0c1 a4 a0 a7 a3 a6 a2 a5 a1 a4 a0 a15c1023 a8c3 a8c2 a8c1 a12 a8 a15 a11 a14 a10 a13 a9 a12 a8 a23c1023 a16c3 a16c2 a16c1 a20 a16 a23 a19 a22 a18 a21 a17 a20 a16 a31c1023 a24c3 a24c2 a24c1 a28 a24 a31 a27 a30 a26 a29 a25 a28 a24 …………………………………………… 128s x freq ch 1 128 samples of the frequency channel 0 F engine
Page 1 and 2: A Digital Backend Architecture for
Page 3 and 4: Contents Preface 3 Chapter I: Digit
Page 5 and 6: Digital Backends CASPER group The t
Page 7 and 8: These blocks leverage the Xilinx IP
Page 9 and 10: V V V V V V V V V V V V V V V V Inp
Page 11 and 12: F engine ROACH-1 40 Mbps ADC 64ch 1
Page 13 and 14: 40 Mbps ADC 64ch PFB Reorder FFT 16
Page 15 and 16: 0 - 3 4 - 7 8 - 11 28 - 31 ….....
Page 17 and 18: A real-sampled biplex FFT, with out
Page 19 and 20: 40 Mbps ADC 64ch PFB Reorder FFT 16
Page 21 and 22: Phase corrections preparations 20 c
Page 23 and 24: X engine expects groups of a single
Page 37 and 38: 32 bit x 64t each antennas interliv
Page 39 and 40: …packaging… data in: 128 sample
Page 41 and 42: Phase corrections done! 40 Phase co
Page 43 and 44: The Fourier Imager (S engine) expec
Page 45 and 46: t 0 t 1 t 1024 t end a0c0 a0c1 a1c0
Page 47: The Fourier Imager (S engine) expec
Page 51 and 52: Control Signals and Registers 50 SY
Page 53 and 54: Control Signals and Registers 52 AD
Page 55 and 56: Control Signals and Registers X_SNA
Page 57 and 58: Control Signals and Registers STATU
Page 59 and 60: Getting data from F engine 58 Accep
Page 61 and 62: Getting data from F engine 60 Decod
Page 63 and 64: X engines 62 Slice: n_xeng_bits - s
Page 65 and 66: X engines 64 TVG block: Test Vector
Page 67 and 68: CASPER Windowed X-Engine block 66 D
Page 69 and 70: CASPER Windowed X-Engine block The
Page 71 and 72: X engines 70 Sync and Valid signals
Page 73 and 74: Vector Accumulator and Packetizer V
Page 75 and 76: Sending data over 10GbE of the 2 X-
Page 77 and 78: Main Control Signals and Registers
Page 79 and 80: Main Control Signals and Registers
Page 81 and 82: Getting data from F engine 80 Accep
Page 83 and 84: Buffering and preparing data for Sp
Page 85 and 86: Spatial FFT - Stage 1 84 Each anten
Page 87 and 88: Spatial FFT - Stage 1 86 Subband ma
Page 89 and 90: Spatial FFT - Stage 1 88 Keep contr
Page 91 and 92: Spatial FFT - Tranpose 90 Transpose
Page 93 and 94: Spatial FFT - Power spectrum 92 Squ
Page 95 and 96: Spatial FFT - Integration 94 Data i
Page 97 and 98: Spatial FFT - Quantization 96 You c
Page 99 and 100:
Main Control Signals and Registers
Page 101 and 102:
Main Control Signals and Registers
Page 103:
Bibliography [1] Parsons, A., et al
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A Digital Backend Architecture for Fourier Imaging

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