A Digital Backend Architecture for Fourier Imaging
A Digital Backend Architecture for Fourier Imaging
A Digital Backend Architecture for Fourier Imaging
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with a peer-to-peer XAUI protocol, while the data will be passed to the workstation encapsulated<br />
in UDP packets.<br />
Figure 1: one of the ROACH boards at Medicina without the chassis.<br />
Programming and Libraries<br />
The System Generator is a DSP design tool from Xilinx that enables the use of The Mathworks<br />
model-based design environment Simulink <strong>for</strong> FPGA design. Over 90 DSP building blocks are<br />
provided in the Xilinx DSP blockset <strong>for</strong> Simulink. These blocks include the common DSP building<br />
blocks such as adders, multipliers and registers. Also included are a set of complex DSP building<br />
blocks such as <strong>for</strong>ward error correction blocks, FFTs, filters and memories.<br />
Figure 2: A view of some XILINX blocks used in Simulink<br />
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