A Digital Backend Architecture for Fourier Imaging

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X engine expects groups of a single channel and a single antenna 27 Every 8 column the same frequency channel is referring to the next spectra, next channels are grouped by 8x128 (=1024=2^10) t 0 t 1 t 2 t 8 t 2^10 t 2^20 a0c0 a1c0 a2c0 a0c0 a0c1 a7c1023 Μ T = a8c0 a9c0 a10c0 a8c0 a8c1 a15c1023 a16c0 a17c0 a18c0 a16c0 a16c1 a23c1023 a24c0 a25c0 a26c0 a24c0 a24c1 a31c1023 X0 X2^10 X(2^10)*2 X(2^10)*8 X1 X(2^20) F engine
X engine expects groups of a single channel and a single antenna 28 The reorder map at this stage groups data by 8 (let’s call M T8 ) [0 8 16 24 32 … 1008 1016 1 9 17 … 999 1007 1015 1023] There<strong>for</strong>e grouping same channels of different acquisitions t 0 t 1 t 2 t 127 t 128 t 2^10 t 2^20 a0c0 a0c0 a0c0 a0c0 a1c0 a0c1 a7c1023 Μ T8 = a8c0 a8c0 a8c0 a8c0 a9c0 a8c1 a15c1023 a16c0 a16c0 a16c0 a16c0 a17c0 a16c1 a23c1023 a24c0 a24c0 a24c0 a24c0 a25c0 a24c1 a31c1023 X0 X(2^10)*8 X(2^10)*16 X(2^10)*1016 X2^10 X1 X(2^20) F engine
Page 1 and 2: A Digital Backend Architecture for
Page 3 and 4: Contents Preface 3 Chapter I: Digit
Page 5 and 6: Digital Backends CASPER group The t
Page 7 and 8: These blocks leverage the Xilinx IP
Page 9 and 10: V V V V V V V V V V V V V V V V Inp
Page 11 and 12: F engine ROACH-1 40 Mbps ADC 64ch 1
Page 13 and 14: 40 Mbps ADC 64ch PFB Reorder FFT 16
Page 15 and 16: 0 - 3 4 - 7 8 - 11 28 - 31 ….....
Page 17 and 18: A real-sampled biplex FFT, with out
Page 19 and 20: 40 Mbps ADC 64ch PFB Reorder FFT 16
Page 21 and 22: Phase corrections preparations 20 c
Page 23 and 24: X engine expects groups of a single
Page 27: X engine expects groups of a single
Page 37 and 38: 32 bit x 64t each antennas interliv
Page 39 and 40: …packaging… data in: 128 sample
Page 41 and 42: Phase corrections done! 40 Phase co
Page 43 and 44: The Fourier Imager (S engine) expec
Page 45 and 46: t 0 t 1 t 1024 t end a0c0 a0c1 a1c0
Page 47 and 48: The Fourier Imager (S engine) expec
Page 49 and 50: S engine data order t 2^20 t 3072 t
Page 51 and 52: Control Signals and Registers 50 SY
Page 53 and 54: Control Signals and Registers 52 AD
Page 55 and 56: Control Signals and Registers X_SNA
Page 57 and 58: Control Signals and Registers STATU
Page 59 and 60: Getting data from F engine 58 Accep
Page 61 and 62: Getting data from F engine 60 Decod
Page 63 and 64: X engines 62 Slice: n_xeng_bits - s
Page 65 and 66: X engines 64 TVG block: Test Vector
Page 67 and 68: CASPER Windowed X-Engine block 66 D
Page 69 and 70: CASPER Windowed X-Engine block The
Page 71 and 72: X engines 70 Sync and Valid signals
Page 73 and 74: Vector Accumulator and Packetizer V
Page 75 and 76: Sending data over 10GbE of the 2 X-
Page 77 and 78: Main Control Signals and Registers
Page 79 and 80:
Main Control Signals and Registers
Page 81 and 82:
Getting data from F engine 80 Accep
Page 83 and 84:
Buffering and preparing data for Sp
Page 85 and 86:
Spatial FFT - Stage 1 84 Each anten
Page 87 and 88:
Spatial FFT - Stage 1 86 Subband ma
Page 89 and 90:
Spatial FFT - Stage 1 88 Keep contr
Page 91 and 92:
Spatial FFT - Tranpose 90 Transpose
Page 93 and 94:
Spatial FFT - Power spectrum 92 Squ
Page 95 and 96:
Spatial FFT - Integration 94 Data i
Page 97 and 98:
Spatial FFT - Quantization 96 You c
Page 99 and 100:
Page 101 and 102:
Page 103:
Bibliography [1] Parsons, A., et al
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A Digital Backend Architecture for Fourier Imaging

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