FLEX 10KE Embedded Programmable Logic Device Data Sheet

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FLEX 10KE Embedded Programmable Logic Devices Data Sheet Figure 14. FLEX 10KE Interconnect Resources See Figure 17 for details. I/O Element (IOE) IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE Row Interconnect LAB A1 LAB A2 LAB A3 See Figure 16 for details. Column Interconnect LAB A5 LAB A4 IOE IOE IOE IOE LAB B1 LAB B2 LAB B3 Cascade & Carry Chains LAB B5 LAB B4 IOE IOE IOE IOE IOE IOE I/O Element An IOE contains a bidirectional I/O buffer and a register that can be used either as an input register for external data that requires a fast setup time, or as an output register for data that requires fast clock-to-output performance. In some cases, using an LE register for an input register will result in a faster setup time than using an IOE register. IOEs can be used as input, output, or bidirectional pins. For bidirectional registered I/O implementation, the output register should be in the IOE, and the data input and output enable registers should be LE registers placed adjacent to the bidirectional pin. The Altera Compiler uses the programmable inversion option to invert signals from the row and column interconnect automatically where appropriate. Figure 15 shows the bidirectional I/O registers. 30 Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet Figure 15. FLEX 10KE Bidirectional I/O Registers Row and Column Interconnect 2 Dedicated Clock Inputs 4 Dedicated Inputs Peripheral Control Bus 4 2 12 OE Register D Q VCC ENA CLRN OE[7..0] VCC Chip-Wide Reset (1) Programmable Delay Chip-Wide Output Enable VCC Output Register (2) D Q CLK[1..0] CLK[3..2] VCC ENA[5..0] ENA CLRN Open-Drain Output Slew-Rate Control VCC CLRN[1..0] VCC Chip-Wide Reset Input Register (2) D Q ENA CLRN Chip-Wide Reset Note: (1) All FLEX 10KE devices (except the EPF10K50E and EPF10K200E devices) have a programmable input delay buffer on the input path. Altera Corporation 31
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